[PATCH 03/15] arm64: dts: allwinner: h616: add NAND controller
From: Richard Genoud <richard.genoud@bootlin.com>
Date: 2025-10-10 08:41:38
Also in:
linux-devicetree, linux-sunxi, lkml
Subsystem:
arm/allwinner sunxi soc support, the rest · Maintainers:
Chen-Yu Tsai, Jernej Skrabec, Samuel Holland, Linus Torvalds
The H616 has a NAND controller quite similar to the A10/A23 ones, but with some register differences, more clocks (for ECC and MBUS), more ECC strengths, so this requires a new compatible string. This patch adds the NAND controller node and pins in the device tree. Signed-off-by: Richard Genoud <richard.genoud@bootlin.com> --- .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
index ceedae9e399b..60626eba7f7c 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi@@ -278,6 +278,37 @@ ir_rx_pin: ir-rx-pin { function = "ir_rx"; }; + nand_pins: nand-pins { + pins = "PC0", "PC1", "PC2", "PC5", "PC8", "PC9", + "PC10", "PC11", "PC12", "PC13", "PC14", + "PC15", "PC16"; + function = "nand0"; + }; + + nand_cs0_pin: nand-cs0-pin { + pins = "PC4"; + function = "nand0"; + bias-pull-up; + }; + + nand_cs1_pin: nand-cs1-pin { + pins = "PC3"; + function = "nand0"; + bias-pull-up; + }; + + nand_rb0_pin: nand-rb0-pin { + pins = "PC6"; + function = "nand0"; + bias-pull-up; + }; + + nand_rb1_pin: nand-rb1-pin { + pins = "PC7"; + function = "nand0"; + bias-pull-up; + }; + mmc0_pins: mmc0-pins { pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
@@ -440,6 +471,25 @@ mmc2: mmc@4022000 { #size-cells = <0>; }; + nfc: nand-controller@4011000 { + compatible = "allwinner,sun50i-h616-nand-controller"; + reg = <0x04011000 0x1000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_NAND>, <&ccu CLK_NAND0>, + <&ccu CLK_NAND1>, <&ccu CLK_MBUS_NAND>; + clock-names = "ahb", "mod", "ecc", "mbus"; + resets = <&ccu RST_BUS_NAND>; + reset-names = "ahb"; + dmas = <&dma 10>; + dma-names = "rxtx"; + pinctrl-names = "default"; + pinctrl-0 = <&nand_pins>, <&nand_cs0_pin>, + <&nand_cs1_pin>, <&nand_rb0_pin>, + <&nand_rb1_pin>; + #address-cells = <1>; + #size-cells = <0>; + }; + uart0: serial@5000000 { compatible = "snps,dw-apb-uart"; reg = <0x05000000 0x400>;
--
2.47.3