[PATCH 14/16] arm64: dts: rockchip: add rga3 dt nodes
From: Sven Püschel <hidden>
Date: 2025-10-07 08:33:01
Also in:
linux-devicetree, linux-media, linux-rockchip, lkml
Subsystem:
the rest · Maintainer:
Linus Torvalds
Add devicetree nodes for the RGA3 peripheral in the RK3588. They are based on the vendor downstream device nodes, but were adjusted to work with the rockchip-rga and iommu driver kernel. Signed-off-by: Sven Püschel <redacted> --- arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 46 +++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 70f03e68ba550d6b9142131dcca86e8ded36e2f1..08885d9c19e0c104ab0f723ec161b83998cfb9c7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi@@ -1172,6 +1172,52 @@ rga: rga@fdb80000 { power-domains = <&power RK3588_PD_VDPU>; }; + rga3_core0: rga@fdb60000 { + compatible = "rockchip,rk3588-rga3"; + reg = <0x0 0xfdb60000 0x0 0x200>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "rga3_core0_irq"; + clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>, <&cru CLK_RGA3_0_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA3_0_CORE>, <&cru SRST_A_RGA3_0>, <&cru SRST_H_RGA3_0>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3588_PD_RGA30>; + iommus = <&rga3_0_mmu>; + }; + + rga3_0_mmu: iommu@fdb60f00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdb60f00 0x0 0x100>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RGA3_0>, <&cru HCLK_RGA3_0>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RGA30>; + }; + + rga3_core1: rga@fdb70000 { + compatible = "rockchip,rk3588-rga3"; + reg = <0x0 0xfdb70000 0x0 0x200>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "rga3_core1_irq"; + clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>, <&cru CLK_RGA3_1_CORE>; + clock-names = "aclk", "hclk", "sclk"; + resets = <&cru SRST_RGA3_1_CORE>, <&cru SRST_A_RGA3_1>, <&cru SRST_H_RGA3_1>; + reset-names = "core", "axi", "ahb"; + power-domains = <&power RK3588_PD_RGA31>; + iommus = <&rga3_1_mmu>; + }; + + rga3_1_mmu: iommu@fdb70f00 { + compatible = "rockchip,rk3588-iommu", "rockchip,rk3568-iommu"; + reg = <0x0 0xfdb70f00 0x0 0x100>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru ACLK_RGA3_1>, <&cru HCLK_RGA3_1>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_RGA31>; + }; + vepu121_0: video-codec@fdba0000 { compatible = "rockchip,rk3588-vepu121"; reg = <0x0 0xfdba0000 0x0 0x800>;
--
2.51.0