RE: [PATCH 2/3] dmaengine: xilinx_dma: Enable transfer chaining by removing idle restriction
From: "Pandey, Radhey Shyam" <radhey.shyam.pandey@amd.com>
Date: 2025-09-29 05:44:41
Also in:
dmaengine, lkml
[AMD Official Use Only - AMD Internal Distribution Only]
-----Original Message----- From: Suraj Gupta <redacted> Sent: Wednesday, September 17, 2025 7:06 PM To: vkoul@kernel.org; Pandey, Radhey Shyam <radhey.shyam.pandey@amd.com>; Simek, Michal [off-list ref] Cc: dmaengine@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux- kernel@vger.kernel.org Subject: [PATCH 2/3] dmaengine: xilinx_dma: Enable transfer chaining by removing idle restriction Remove the restrictive idle check in xilinx_dma_start_transfer() that prevented new transfers from being queued when the channel was busy. Additionally, only update the CURDESC register when the active list is empty to avoid interfering with transfers already in progress. When the active list contains transfers, the hardware tail pointer extension mechanism handles chaining automatically.
As we already have changes ready for MCDMA - please merge it in v2. Both axidma /mcdma will support axistream connected.
quoted hunk ↗ jump to hunk
Signed-off-by: Suraj Gupta <redacted> --- drivers/dma/xilinx/xilinx_dma.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index9f416eae33d0..7211c394cdca 100644--- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c@@ -1548,9 +1548,6 @@ static void xilinx_dma_start_transfer(structxilinx_dma_chan *chan) if (list_empty(&chan->pending_list)) return; - if (!chan->idle) - return; - head_desc = list_first_entry(&chan->pending_list, struct xilinx_dma_tx_descriptor, node); tail_desc = list_last_entry(&chan->pending_list,@@ -1567,7 +1564,7 @@ static void xilinx_dma_start_transfer(structxilinx_dma_chan *chan) dma_ctrl_write(chan, XILINX_DMA_REG_DMACR, reg); } - if (chan->has_sg) + if (chan->has_sg && list_empty(&chan->active_list)) xilinx_write(chan, XILINX_DMA_REG_CURDESC, head_desc->async_tx.phys); reg &= ~XILINX_DMA_CR_DELAY_MAX; -- 2.25.1