On 05/09/25 10:27, Kumar, Udit wrote:
On 9/4/2025 7:16 PM, Akashdeep Kaur wrote:
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Hi Udit,
On 04/09/25 18:06, Kumar, Udit wrote:
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#define PULLTYPESEL_SHIFT (17)
#define RXACTIVE_SHIFT (18)
+#define DRV_STR_SHIFT (19)
referring to above TRM mentioned in commit message
Bit 20-19 are for DRV_STR, and description says
0 - Default
1 - Reserved
2 - Reserved
3 - Reserved
Not sure, is there some additional document to be referred for
PIN_DRIVE_STRENGTH
This information will be updated in TRM in coming cycles.
Sorry ,
can not ack before TRM update
The information can be found at https://www.ti.com/lit/ug/spruj83b/
spruj83b.pdf in Table 14-8769. Description Of The Pad Configuration
Register Bit
Then please give correct reference in commit message
Updated the commit message!
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+#define DS_ISO_OVERRIDE_SHIFT (22)
+#define DS_ISO_BYPASS_EN_SHIFT (23)
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/* Default mux configuration for gpio-ranges to use with pinctrl */
#define PIN_GPIO_RANGE_IOPAD (PIN_INPUT | 7)
Regards,
Akashdeep Kaur
Thanks,
Akashdeep Kaur