@@ -31,6 +31,7 @@ struct dw_csi2_regs {
 	u32	dphy_rstz;
 	u32	resetn;
 	u32	phy_state;
+	u32	phy_stopstate;
 	u32	data_ids_1;
 	u32	data_ids_2;
 	u32	err1;

@@ -86,6 +87,7 @@ static const struct dw_csi2_regs dw_csi2_v150 = {
 	.phy_shutdownz = DW_REG(0x40),
 	.dphy_rstz = DW_REG(0x44),
 	.phy_state = DW_REG(0x48),
+	.phy_stopstate = DW_REG(0x4c),
 	.phy_tst_ctrl0 = DW_REG(0x50),
 	.phy_tst_ctrl1 = DW_REG(0x54),
 	.int_st_dphy_fatal = DW_REG(0xe0),

@@ -147,10 +149,13 @@ readl((csi2)->base + ((csi2)->regs->__name & ~DW_REG_EXIST)) : \
 dw_csi2_reg_err(csi2, #__name))
 
 #define PHY_STATE_STOPSTATEDATA_BIT	4
+#define PHY_STATE_STOPSTATEDATA_BIT_V150	0
 #define PHY_STATE_STOPSTATEDATA(n)	BIT(PHY_STATE_STOPSTATEDATA_BIT + (n))
 #define PHY_STATE_RXCLKACTIVEHS	BIT(8)
+#define PHY_STATE_RXCLKACTIVEHS_V150	BIT(17)
 #define PHY_STATE_RXULPSCLKNOT	BIT(9)
 #define PHY_STATE_STOPSTATECLK	BIT(10)
+#define PHY_STATE_STOPSTATECLK_V150		BIT(16)
 
 #define DPHY_TEST_CTRL0_TEST_CLR		BIT(0)
 #define DPHY_TEST_CTRL0_TEST_CLKEN	BIT(1)

@@ -289,7 +294,8 @@ static int __maybe_unused csi2_dphy_wait_ulp(struct dw_mipi_csi2_dev *csi2)
 }
 
 /* Waits for low-power LP-11 state on data and clock lanes. */
-static void csi2_dphy_wait_stopstate(struct dw_mipi_csi2_dev *csi2, unsigned int lanes)
+static void csi2_dphy_wait_stopstate_v0(struct dw_mipi_csi2_dev *csi2,
+					unsigned int lanes)
 {
 	u32 mask, reg;
 	int ret;

@@ -303,13 +309,43 @@ static void csi2_dphy_wait_stopstate(struct dw_mipi_csi2_dev *csi2, unsigned int
 	}
 }
 
+static void csi2_dphy_wait_stopstate_v150(struct dw_mipi_csi2_dev *csi2,
+					  unsigned int lanes)
+{
+	u32 mask, reg;
+	int ret;
+
+	mask = PHY_STATE_STOPSTATECLK_V150 | (((1 << lanes) - 1) <<
+	       PHY_STATE_STOPSTATEDATA_BIT_V150);
+
+	ret = read_poll_timeout(dw_readl, reg, (reg & mask) == mask, 0, 500000,
+				0, csi2, phy_stopstate);
+	if (ret) {
+		v4l2_warn(&csi2->sd, "LP-11 wait timeout, likely a sensor driver bug, expect capture failures.\n");
+		v4l2_warn(&csi2->sd, "phy_state = 0x%08x\n", reg);
+	}
+}
+
+static void csi2_dphy_wait_stopstate(struct dw_mipi_csi2_dev *csi2,
+				     unsigned int lanes)
+{
+	if (csi2->regs == &dw_csi2_v0)
+		return csi2_dphy_wait_stopstate_v0(csi2, lanes);
+
+	csi2_dphy_wait_stopstate_v150(csi2, lanes);
+}
+
 /* Wait for active clock on the clock lane. */
 static int csi2_dphy_wait_clock_lane(struct dw_mipi_csi2_dev *csi2)
 {
+	u32 mask;
 	u32 reg;
 	int ret;
 
-	ret = read_poll_timeout(dw_readl, reg, (reg & PHY_STATE_RXCLKACTIVEHS),
+	mask = csi2->regs == &dw_csi2_v0 ?  PHY_STATE_RXCLKACTIVEHS :
+					    PHY_STATE_RXCLKACTIVEHS_V150;
+
+	ret = read_poll_timeout(dw_readl, reg, (reg & mask),
 				0, 500000, 0, csi2, phy_state);
 	if (ret) {
 		v4l2_err(&csi2->sd, "clock lane timeout, phy_state = 0x%08x\n",