[PATCH v3 23/31] media: synopsys: csi2: Add register prefix to register field definitions
From: Frank Li <Frank.Li@nxp.com>
Date: 2025-08-21 20:18:35
Also in:
imx, linux-devicetree, linux-media, linux-phy, linux-staging, lkml
Subsystem:
media input infrastructure (v4l/dvb), the rest · Maintainers:
Mauro Carvalho Chehab, Linus Torvalds
Add register prefix to register field definitions to improve readability. No functional change. Signed-off-by: Frank Li <Frank.Li@nxp.com> --- drivers/media/platform/synopsys/mipi-csi2.c | 30 ++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/drivers/media/platform/synopsys/mipi-csi2.c b/drivers/media/platform/synopsys/mipi-csi2.c
index 5435b58de55d21aa957fc635c950ba2ae25a8dcc..d6eb666646b916c2609a279f8badc1e8af557121 100644
--- a/drivers/media/platform/synopsys/mipi-csi2.c
+++ b/drivers/media/platform/synopsys/mipi-csi2.c@@ -146,16 +146,16 @@ dw_csi2_reg_err((csi2), #__name)) readl((csi2)->base + ((csi2)->regs->__name & ~DW_REG_EXIST)) : \ dw_csi2_reg_err(csi2, #__name)) -#define PHY_STOPSTATEDATA_BIT 4 -#define PHY_STOPSTATEDATA(n) BIT(PHY_STOPSTATEDATA_BIT + (n)) -#define PHY_RXCLKACTIVEHS BIT(8) -#define PHY_RXULPSCLKNOT BIT(9) -#define PHY_STOPSTATECLK BIT(10) +#define PHY_STATE_STOPSTATEDATA_BIT 4 +#define PHY_STATE_STOPSTATEDATA(n) BIT(PHY_STATE_STOPSTATEDATA_BIT + (n)) +#define PHY_STATE_RXCLKACTIVEHS BIT(8) +#define PHY_STATE_RXULPSCLKNOT BIT(9) +#define PHY_STATE_STOPSTATECLK BIT(10) -#define PHY_TESTCLR BIT(0) -#define PHY_TESTCLK BIT(1) +#define DPHY_TEST_CTRL0_TEST_CLR BIT(0) +#define DPHY_TEST_CTRL0_TEST_CLKEN BIT(1) -#define PHY_TESTEN BIT(16) +#define DPHY_TEST_CTRL1_TEST_EN BIT(16) #define sd_to_dev sd_to_dw_mipi_csi2_dev
@@ -235,20 +235,20 @@ static int dw_mipi_csi2_phy_write(struct dw_mipi_tstif *tstif, struct dw_mipi_csi2_dev *csi2 = container_of(tstif, struct dw_mipi_csi2_dev, tstif); /* Clear PHY test interface */ - dw_writel(csi2, PHY_TESTCLR, phy_tst_ctrl0); + dw_writel(csi2, DPHY_TEST_CTRL0_TEST_CLR, phy_tst_ctrl0); dw_writel(csi2, 0x0, phy_tst_ctrl1); dw_writel(csi2, 0x0, phy_tst_ctrl0); /* Raise test interface strobe signal */ - dw_writel(csi2, PHY_TESTCLK, phy_tst_ctrl0); + dw_writel(csi2, DPHY_TEST_CTRL0_TEST_CLKEN, phy_tst_ctrl0); /* Configure address write on falling edge and lower strobe signal */ - dw_writel(csi2, PHY_TESTEN | test_code, phy_tst_ctrl1); + dw_writel(csi2, DPHY_TEST_CTRL1_TEST_EN | test_code, phy_tst_ctrl1); dw_writel(csi2, 0x0, phy_tst_ctrl0); /* Configure data write on rising edge and raise strobe signal */ dw_writel(csi2, test_data, phy_tst_ctrl1); - dw_writel(csi2, PHY_TESTCLK, phy_tst_ctrl0); + dw_writel(csi2, DPHY_TEST_CTRL0_TEST_CLKEN, phy_tst_ctrl0); /* Clear strobe signal */ dw_writel(csi2, 0x0, phy_tst_ctrl0);
@@ -271,7 +271,7 @@ static int __maybe_unused csi2_dphy_wait_ulp(struct dw_mipi_csi2_dev *csi2) int ret; /* wait for ULP on clock lane */ - ret = read_poll_timeout(dw_readl, reg, !(reg & PHY_RXULPSCLKNOT), + ret = read_poll_timeout(dw_readl, reg, !(reg & PHY_STATE_RXULPSCLKNOT), 0, 500000, 0, csi2, phy_state); if (ret) { v4l2_err(&csi2->sd, "ULP timeout, phy_state = 0x%08x\n", reg);
@@ -294,7 +294,7 @@ static void csi2_dphy_wait_stopstate(struct dw_mipi_csi2_dev *csi2, unsigned int u32 mask, reg; int ret; - mask = PHY_STOPSTATECLK | (((1 << lanes) - 1) << PHY_STOPSTATEDATA_BIT); + mask = PHY_STATE_STOPSTATECLK | (((1 << lanes) - 1) << PHY_STATE_STOPSTATEDATA_BIT); ret = read_poll_timeout(dw_readl, reg, (reg & mask) == mask, 0, 500000, 0, csi2, phy_state); if (ret) {
@@ -309,7 +309,7 @@ static int csi2_dphy_wait_clock_lane(struct dw_mipi_csi2_dev *csi2) u32 reg; int ret; - ret = read_poll_timeout(dw_readl, reg, (reg & PHY_RXCLKACTIVEHS), + ret = read_poll_timeout(dw_readl, reg, (reg & PHY_STATE_RXCLKACTIVEHS), 0, 500000, 0, csi2, phy_state); if (ret) { v4l2_err(&csi2->sd, "clock lane timeout, phy_state = 0x%08x\n",
--
2.34.1