On Wed Aug 13, 2025 at 1:42 PM CDT, Nishanth Menon wrote:
On 12:56-20250813, Randolph Sapp wrote:
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+ reg = <0x00 0x0fd80000 0x00 0x80000>;
+ clocks = <&k3_clks 237 1>;
+ clock-names = "core";
+ assigned-clocks = <&k3_clks 237 1>;
+ assigned-clock-rates = <800000000>;
btw, as per https://www.ti.com/lit/ds/symlink/tda4aen-q1.pdf (page 86)
720MHz when vdd_core is 0.75v (default)
and 800MHz when vdd_core is 0.85v
0.85v is set in the board dts and higher OPPs are enabled depending on
board capability.
You might want to check the assigned-clock-rates based on data sheet,
default should'nt need a assigned-clock-rate.
Are you suggesting that we set assigned-clock-rates in the board dts instead, or
do you just want to do away with assigned-clock-rates in general and eat the
perf difference?