[PATCH 2/5] arm64: dts: imx8ulp: Add CSI and ISI Nodes
From: <hidden>
Date: 2025-08-12 08:21:30
Also in:
imx, linux-devicetree, linux-media, lkml
Subsystem:
arm/freescale imx / mxc arm architecture, the rest · Maintainers:
Frank Li, Sascha Hauer, Linus Torvalds
From: Guoniu Zhou <redacted> The CSI-2 in the i.MX8ULP is almost identical to the version present in the i.MX8QXP/QM and is routed to the ISI. Add both the ISI and CSI nodes and mark them as disabled by default since capture is dependent on an attached camera. Signed-off-by: Guoniu Zhou <redacted> --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 67 ++++++++++++++++++++++ 1 file changed, 67 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
index 2562a35286c2..71abc2a3d505 100644
--- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi@@ -7,6 +7,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/power/imx8ulp-power.h> +#include <dt-bindings/reset/imx8ulp-pcc-reset.h> #include <dt-bindings/thermal/thermal.h> #include "imx8ulp-pinfunc.h"
@@ -840,6 +841,72 @@ spdif: spdif@2dab0000 { dma-names = "rx", "tx"; status = "disabled"; }; + + isi: isi@2dac0000 { + compatible = "fsl,imx8ulp-isi"; + reg = <0x2dac0000 0x10000>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&pcc5 IMX8ULP_CLK_ISI>, + <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>; + clock-names = "axi", "apb"; + power-domains = <&scmi_devpd IMX8ULP_PD_ISI>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + isi_in: endpoint { + remote-endpoint = <&mipi_csi_out>; + }; + }; + }; + }; + + mipi_csi: csi@2daf0000 { + compatible = "fsl,imx8ulp-mipi-csi2"; + reg = <0x2daf0000 0x10000>, + <0x2dad0000 0x10000>; + clocks = <&pcc5 IMX8ULP_CLK_CSI>, + <&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>, + <&pcc5 IMX8ULP_CLK_CSI_CLK_UI>, + <&pcc5 IMX8ULP_CLK_CSI_REGS>; + clock-names = "core", "esc", "ui", "pclk"; + assigned-clocks = <&pcc5 IMX8ULP_CLK_CSI>, + <&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>, + <&pcc5 IMX8ULP_CLK_CSI_CLK_UI>, + <&pcc5 IMX8ULP_CLK_CSI_REGS>; + assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV1>, + <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV2>, + <&cgc2 IMX8ULP_CLK_PLL4_PFD0_DIV1>; + assigned-clock-rates = <200000000>, + <80000000>, + <100000000>, + <79200000>; + power-domains = <&scmi_devpd IMX8ULP_PD_MIPI_CSI>; + resets = <&pcc5 PCC5_CSI_SWRST>, + <&pcc5 PCC5_CSI_REGS_SWRST>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + + mipi_csi_out: endpoint { + remote-endpoint = <&isi_in>; + }; + }; + }; + }; }; gpiod: gpio@2e200000 {
--
2.34.1