RE: [PATCH] mmc: sdhci-of-arasan: Ensure CD logic stabilization before power-up

[AMD Official Use Only - AMD Internal Distribution Only]

Hi Prasanna Kumar,

-----Original Message-----
From: Prasanna Kumar T S M <redacted>
Sent: Friday, August 1, 2025 6:34 PM
To: Potthuri, Sai Krishna <sai.krishna.potthuri@amd.com>; Adrian Hunter
[off-list ref]; Simek, Michal [off-list ref]; Ulf
Hansson [off-list ref]
Cc: linux-mmc@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
kernel@vger.kernel.org; git (AMD-Xilinx) [off-list ref];
saikrishna12468@gmail.com
Subject: Re: [PATCH] mmc: sdhci-of-arasan: Ensure CD logic stabilization before
power-up

Hi Sai Krishna,

On 25-07-2025 11:19, Potthuri, Sai Krishna wrote:

quoted

quoted

Will this work with all Arasan variants?

Yes, this is expected to work across all Arasan variants that comply with the

standard

quoted

SDHCI register definitions. The SDHCI_CD_STABLE bit is defined in both the
standard SDHCI specification and Arasan's user guide.

As SDHCI_CD_STABLE bit is defined in SDHCI specification, why are you
making a driver specific fix? Is this problem specific to Arasan eMMC?
If not, does it make sense to make this a framework level change instead
of a driver specific change?

Given that you are planning to add a quirk, doing this in common code
would be better.

Agree, with the quirk approach we can move the logic to framework(sdhci.c) and
make it as a common code.
I will move the logic to sdhci_set_power_noreg() function.

Regards
Sai Krishna

quoted

On Xilinx/AMD Versal and ZynqMP platforms, the CD stable bit is typically set

within

quoted

a few milliseconds. However, to be on the safer side and ensure compatibility

across

quoted

all Arasan variants, a timeout of 1 second is added.
Please let me know if you prefer to increase the timeout or if this logic should be
enabled by a platform specific quirk.

Thanks,

Prasanna Kumar