Hi Sai Krishna,

On 25-07-2025 11:19, Potthuri, Sai Krishna wrote:

quoted

Will this work with all Arasan variants?

Yes, this is expected to work across all Arasan variants that comply with the standard
SDHCI register definitions. The SDHCI_CD_STABLE bit is defined in both the
standard SDHCI specification and Arasan's user guide.

As SDHCI_CD_STABLE bit is defined in SDHCI specification, why are you 
making a driver specific fix? Is this problem specific to Arasan eMMC? 
If not, does it make sense to make this a framework level change instead 
of a driver specific change?

Given that you are planning to add a quirk, doing this in common code 
would be better.

On Xilinx/AMD Versal and ZynqMP platforms, the CD stable bit is typically set within
a few milliseconds. However, to be on the safer side and ensure compatibility across
all Arasan variants, a timeout of 1 second is added.
Please let me know if you prefer to increase the timeout or if this logic should be
enabled by a platform specific quirk.

Thanks,

Prasanna Kumar