Re: [PATCH v3 1/2] dt-bindings: interrupt-controller: aspeed: Add parent node compatibles and refine documentation

On 22/07/2025 11:51, Ryan Chen wrote:

The AST2700 SoC contains two independent top-level interrupt controllers
(INTC0 and INTC1), each responsible for handling different peripheral
groups and occupying separate register spaces. Above them, PSP(CA35) GIC
controller acts as the root interrupt aggregator. Accurately describing
this hierarchical hardware structure in the device tree requires distinct
compatible strings for the parent nodes of INTC0 and INTC1.

- Adds 'aspeed,ast2700-intc0' and 'aspeed,ast2700-intc1' compatible
 strings for parent interrupt controller nodes. (in addition to the
 existing 'aspeed,ast2700-intc-ic' for child nodes)

I don't understand how this solves your problem at all. Look at old
diagram - is it correct? If not, what makes you think that new diagram
is correct?

What is the meaning of existing binding and existing intc-ic compatible?

- Clarifies the relationship and function of INTC0 parent
 (intc0_0~x: child), INTC1 parent (intc1_0~x: child), and the GIC
 in the documentation.
- Updates block diagrams and device tree examples to illustrate
 the hierarchy and compatible usage.
- Refines documentation and example formatting.

This change allows the device tree and driver to distinguish between
parent (top-level) and child (group) interrupt controller nodes,
enabling more precise driver matching SOC register space allocation.

And how it was not possible before? That's poor argument especially that
DT does not have to ever distinguish that.


Best regards,
Krzysztof