Re: [PATCH v7 01/12] dt-bindings: mfd: add support for the NXP SIUL2 module
From: Frank Li <Frank.li@nxp.com>
Date: 2025-07-10 15:49:27
Also in:
imx, linux-devicetree, linux-gpio, lkml
On Thu, Jul 10, 2025 at 05:20:24PM +0300, Andrei Stefanescu wrote:
Add the dt-bindings for the NXP SIUL2 module which is a multi function device. It can export information about the SoC, configure the pinmux&pinconf for pins and it is also a GPIO controller with interrupt capability.
wrap at 75 chars.
quoted hunk ↗ jump to hunk
Signed-off-by: Andrei Stefanescu <redacted> --- .../bindings/mfd/nxp,s32g2-siul2.yaml | 163 ++++++++++++++++++ 1 file changed, 163 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/nxp,s32g2-siul2.yamldiff --git a/Documentation/devicetree/bindings/mfd/nxp,s32g2-siul2.yaml b/Documentation/devicetree/bindings/mfd/nxp,s32g2-siul2.yaml new file mode 100644 index 000000000000..8ae185b4bc78 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/nxp,s32g2-siul2.yaml@@ -0,0 +1,163 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 NXP +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/nxp,s32g2-siul2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP S32 System Integration Unit Lite2 (SIUL2) + +maintainers: + - Andrei Stefanescu <andrei.stefanescu@oss.nxp.com> + +description: | + SIUL2 is a hardware block which implements pinmuxing, + pinconf, GPIOs (some with interrupt capability) and + registers which contain information about the SoC. + There are generally two SIUL2 modules whose functionality + is grouped together. For example interrupt configuration + registers are part of SIUL2_1 even though interrupts are + also available for SIUL2_0 pins. + + The following register types are exported by SIUL2: + - MIDR (MCU ID Register) - information related to the SoC + - interrupt configuration registers + - MSCR (Multiplexed Signal Configuration Register) - pinmuxing and pinconf + - IMCR (Input Multiplexed Signal Configuration Register)- pinmuxing + - PGPDO (Parallel GPIO Pad Data Out Register) - GPIO output value + - PGPDI (Parallel GPIO Pad Data In Register) - GPIO input value + + Most registers are 32bit wide with the exception of PGPDO/PGPDI which are + 16bit wide. + +properties: + compatible: + oneOf: + - const: nxp,s32g2-siul2 + - items: + - enum: + - nxp,s32g3-siul2 + - const: nxp,s32g2-siul2 + + reg: + minItems: 2 + + reg-names: + items: + - const: siul20 + - const: siul21 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + gpio-ranges: + maxItems: 2 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + nvmem-layout: + $ref: /schemas/nvmem/layouts/nvmem-layout.yaml# + description: + This container may reference an NVMEM layout parser. + +patternProperties: + "-hog(-[0-9]+)?$": + required: + - gpio-hog + + "-pins$": + type: object + additionalProperties: false + + patternProperties: + "-grp[0-9]$": + type: object + allOf: + - $ref: /schemas/pinctrl/pinmux-node.yaml# + - $ref: /schemas/pinctrl/pincfg-node.yaml# + description: + Pinctrl node's client devices specify pin muxes using subnodes, + which in turn use the standard properties below. + + properties: + bias-disable: true + bias-high-impedance: true + bias-pull-up: true + bias-pull-down: true + drive-open-drain: true + input-enable: true + output-enable: true
I remember you needn't mark these as true, default it should be true if use "unevaluatedProperties: false". Can you check if pass dt_binding_check if remove these property?
+ + pinmux: + description: | + An integer array for representing pinmux configurations of + a device. Each integer consists of a PIN_ID and a 4-bit + selected signal source(SSS) as IOMUX setting, which is + calculated as: pinmux = (PIN_ID << 4 | SSS)
Do you have include file to define it? otherwise hex value is not easy understand. Frank
+
+ slew-rate:
+ description: Supported slew rate based on Fmax values (MHz)
+ enum: [83, 133, 150, 166, 208]
+ required:
+ - pinmux
+
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - gpio-controller
+ - "#gpio-cells"
+ - gpio-ranges
+ - interrupts
+ - interrupt-controller
+ - "#interrupt-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ pinctrl@4009c000 {
+ compatible = "nxp,s32g2-siul2";
+ reg = <0x4009c000 0x179c>,
+ <0x44010000 0x17b0>;
+ reg-names = "siul20", "siul21";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&siul2 0 0 102>, <&siul2 112 112 79>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>;
+
+ jtag-pins {
+ jtag-grp0 {
+ pinmux = <0x0>;
+ input-enable;
+ bias-pull-up;
+ slew-rate = <166>;
+ };
+ };
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc-major@0 {
+ reg = <0 0x4>;
+ };
+ };
+ };
+...
--
2.45.2