Thread (15 messages) 15 messages, 5 authors, 2025-07-04

Re: [PATCH 3/5] clk: sunxi-ng: v3s: Fix CSI1 MCLK clock name

From: Icenowy Zheng <hidden>
Date: 2025-07-02 03:10:49
Also in: dri-devel, linux-clk, linux-devicetree, linux-gpio, linux-media, linux-sunxi, lkml

在 2025-07-01星期二的 22:11 +0200,Paul Kocialkowski写道:
quoted hunk ↗ jump to hunk
The CSI1 MCLK clock is reported as "csi-mclk" while it is specific to
CSI1 as the name of the definition indicates. Fix it in the driver.

Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Paul Kocialkowski <paulk@sys-base.io>
---
 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
index d12791b31a9d..86d933d1ac72 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -366,7 +366,7 @@ static const char * const csi_sclk_parents[] = {
"pll-video", "pll-isp" };
 static SUNXI_CCU_M_WITH_MUX_GATE(csi_sclk_clk, "csi-sclk",
csi_sclk_parents,
                                 0x134, 16, 4, 24, 3, BIT(31), 0);
 
-static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk",
csi_mclk_parents,
+static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi1-mclk",
csi_mclk_parents,
                                 0x134, 0, 5, 8, 3, BIT(15), 0);
Yes, there exists csi0-mclk.

Reviewed-By: Icenowy Zheng <redacted>
 
 static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
  
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