On 2/25/25 15:57, Fabrice Gasnier wrote:

On 2/25/25 13:02, Krzysztof Kozlowski wrote:

quoted

On Mon, Feb 24, 2025 at 07:01:46PM +0100, Fabrice Gasnier wrote:

quoted

From: Patrick Delaunay <redacted>

Add the support of the new compatible for STM32MP25 SoC in driver, as
described in Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml
and used in arch/arm64/boot/dts/st/stm32mp251.dtsi.

Signed-off-by: Patrick Delaunay <redacted>
Signed-off-by: Fabrice Gasnier <fabrice.gasnier@foss.st.com>
---
 drivers/clocksource/timer-stm32-lp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clocksource/timer-stm32-lp.c b/drivers/clocksource/timer-stm32-lp.c
index a4c95161cb22..db055348e2cc 100644
--- a/drivers/clocksource/timer-stm32-lp.c
+++ b/drivers/clocksource/timer-stm32-lp.c

@@ -197,6 +197,7 @@ static int stm32_clkevent_lp_probe(struct platform_device *pdev)
 
 static const struct of_device_id stm32_clkevent_lp_of_match[] = {
 	{ .compatible = "st,stm32-lptimer-timer", },
+	{ .compatible = "st,stm32mp25-lptimer-timer", },
 	{},

Same question.

Oops, I just figured out I have missed a change to this driver, to
enable interrupts, in order to comply with the LPTimer spec, starting
with STM32MP25.

E.g. with earlier STM32MP13, STM32MP15 or even STM32H7:
* The LPTIM_IER register must only be modified when the LPTIM is
disabled (ENABLE bit reset to ‘0’)

On STM32MP25:
* The LPTIMx_DIER register must only be modified when the LPTIM is
enabled (ENABLE bit set to 1)

I'll add this as compatible data in next revision.

This is specific behavior, to the new revision of the LPTimer hardware.
It can be read from revision/identification registers. So this new
compatible can be dropped.

I'll remove "st,stm32mp25-lptimer-timer" compatible string in next revision.

Thanks for reviewing,
BR,
Fabrice

Best regards,
Fabrice

quoted

Best regards,
Krzysztof