[PATCH 9/9] arm64: dts: apple: t8015: Add CPU caches
From: Nick Chan <hidden>
Date: 2025-02-20 12:22:51
Also in:
asahi, linux-devicetree, lkml
Subsystem:
arm/apple machine support, the rest · Maintainers:
Sven Peter, Janne Grunau, Linus Torvalds
Add information about CPU caches in Apple A11 SoC. Signed-off-by: Nick Chan <redacted> --- arch/arm64/boot/dts/apple/t8015.dtsi | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/apple/t8015.dtsi b/arch/arm64/boot/dts/apple/t8015.dtsi
index b68647bebd20782ba7a125e670b3264c184b62cd..138073dbac3c5a3ec495b078b3714cf800b471dd 100644
--- a/arch/arm64/boot/dts/apple/t8015.dtsi
+++ b/arch/arm64/boot/dts/apple/t8015.dtsi@@ -63,6 +63,9 @@ cpu_e0: cpu@0 { capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; }; cpu_e1: cpu@1 {
@@ -74,6 +77,9 @@ cpu_e1: cpu@1 { capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; }; cpu_e2: cpu@2 {
@@ -85,6 +91,9 @@ cpu_e2: cpu@2 { capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; }; cpu_e3: cpu@3 {
@@ -96,6 +105,9 @@ cpu_e3: cpu@3 { capacity-dmips-mhz = <633>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache_0>; + i-cache-size = <0x8000>; + d-cache-size = <0x8000>; }; cpu_p0: cpu@10004 {
@@ -107,6 +119,9 @@ cpu_p0: cpu@10004 { capacity-dmips-mhz = <1024>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; }; cpu_p1: cpu@10005 {
@@ -118,6 +133,23 @@ cpu_p1: cpu@10005 { capacity-dmips-mhz = <1024>; enable-method = "spin-table"; device_type = "cpu"; + next-level-cache = <&l2_cache_1>; + i-cache-size = <0x10000>; + d-cache-size = <0x10000>; + }; + + l2_cache_0: l2-cache-0 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x100000>; + }; + + l2_cache_1: l2-cache-1 { + compatible = "cache"; + cache-level = <2>; + cache-unified; + cache-size = <0x800000>; }; };
--
2.48.1