Re: [PATCH v2 2/2] phy: cadence-torrent: Add PCIe multilink + USB with same SSC register config for 100 MHz refclk
From: Siddharth Vadapalli <s-vadapalli@ti.com>
Date: 2025-01-09 12:20:23
Also in:
linux-phy, lkml
On Tue, Jan 07, 2025 at 10:49:38AM +0530, Siddharth Vadapalli wrote:
On Mon, Jan 06, 2025 at 11:05:35PM +0100, Christophe JAILLET wrote:quoted
Le 06/01/2025 à 14:19, Siddharth Vadapalli a écrit :quoted
From: Swapnil Jakhade <redacted> Add register sequences and support for PCIe multilink + USB configuration for 100MHz reference clock. The same SSC is used for both PCIe and USB. Signed-off-by: Swapnil Jakhade <redacted> Co-developed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> ---...quoted
@@ -2513,6 +2517,44 @@ int cdns_torrent_phy_configure_multilink(struct cdns_torrent_phy *cdns_phy) phy_t1 = fns(cdns_phy->protocol_bitmask, 0); phy_t2 = fns(cdns_phy->protocol_bitmask, 1); + + /**Why kernel-doc like start of comment? Only /* ?quoted
+ * PCIe Multilink configuration can be supported along with a + * non-PCIe protocol. The existing limitation associated with + * the standalone PCIe Multilink configuration still remains, + * implying that there can be only two links (subnodes) of the + * PHY type PCIe which constitute the PCIe Multilink. + * + * Such configurations are handled by introducing a new protocol + * namely TYPE_PCIE_ML. Both of the PCIe links which have the + * protocol as TYPE_PCIE shall be treated as though the protocol + * corresponding to them is TYPE_PCIE_ML only for the sake of + * configuring the SERDES. + * + * PCIe Multilink configuration can be identified by checking if + * there are exactly two links with phy_type set to TYPE_PCIE. + * phy_t1 and phy_t2 are modified in such cases to support the + * PCIe Multilink configuration with a non-PCIe protocol. + */...quoted
@@ -3134,6 +3180,37 @@ static void cdns_torrent_phy_remove(struct platform_device *pdev) cdns_torrent_clk_cleanup(cdns_phy); } +/* Multilink PCIe and USB Same SSC link configuration */ +static struct cdns_reg_pairs ml_pcie_usb_link_cmn_regs[] = { + {0x0002, PHY_PLL_CFG}, + {0x8600, CMN_PDIAG_PLL0_CLK_SEL_M0} +};Maybe const could be added here and below?quoted
+ +static struct cdns_reg_pairs ml_pcie_usb_xcvr_diag_ln_regs[] = { + {0x0100, XCVR_DIAG_HSCLK_SEL}, + {0x0013, XCVR_DIAG_HSCLK_DIV}, + {0x0812, XCVR_DIAG_PLLDRC_CTRL} +};I will update this patch based on your feedback in the v3 series. Thank you for the review.
I have posted the v3 series at: https://lore.kernel.org/r/20250109121614.754466-1-s-vadapalli@ti.com/ (local) Regards, Siddharth.