On Mon, Jan 06, 2025 at 11:00:14PM +0100, Christophe JAILLET wrote:

Le 06/01/2025 à 14:19, Siddharth Vadapalli a écrit :

quoted

From: Swapnil Jakhade <redacted>

Add register sequences to support PCIe multilink configuration for 100MHz
reference clock. Maximum two PCIe links are supported.

Signed-off-by: Swapnil Jakhade <redacted>
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---

***NOTE***
Since I don't have the hardware required to validate PCIe Multilink +
USB functionality, kindly *do not merge* this series until it gets a
"Tested-by" tag with proper validation of the functionality.

Regards,
Siddharth.

  drivers/phy/cadence/phy-cadence-torrent.c | 130 +++++++++++++++++++++-
  1 file changed, 129 insertions(+), 1 deletion(-)

diff --git a/drivers/phy/cadence/phy-cadence-torrent.c b/drivers/phy/cadence/phy-cadence-torrent.c
index a281c0dfae97..b0b5f4bdd7e2 100644
--- a/drivers/phy/cadence/phy-cadence-torrent.c
+++ b/drivers/phy/cadence/phy-cadence-torrent.c

[...]

quoted

@@ -3131,6 +3134,101 @@ static void cdns_torrent_phy_remove(struct platform_device *pdev)
  	cdns_torrent_clk_cleanup(cdns_phy);
  }
+/* Multi link PCIe configuration */
+static struct cdns_reg_pairs ml_pcie_link_cmn_regs[] = {
+	{0x0002, PHY_PLL_CFG},
+	{0x0601, CMN_PDIAG_PLL0_CLK_SEL_M0}
+};

I think that some, if not all, of these new struct could be const, as
elsewhere in this file.

Thank you for reviewing the patch and pointing this out. I will change
them to 'const' in the v3 series.

quoted

+
+static struct cdns_reg_pairs ml_pcie_xcvr_diag_ln_regs[] = {
+	{0x0100, XCVR_DIAG_HSCLK_SEL},
+	{0x0001, XCVR_DIAG_HSCLK_DIV},
+	{0x0812, XCVR_DIAG_PLLDRC_CTRL}
+};

Regards,
Siddharth.