[PATCH v5 2/8] clk: qcom: ipq5332: add gpll0_out_aux clock
From: Varadarajan Narayanan <hidden>
Date: 2024-08-29 08:29:30
Also in:
linux-arm-msm, linux-clk, linux-devicetree, linux-pm, lkml, netdev
Subsystem:
arm/qualcomm mailing list, common clk framework, qualcomm clock drivers, the rest · Maintainers:
Stephen Boyd, Brian Masney, Jerome Brunet, Bjorn Andersson, Linus Torvalds
From: Kathiravan Thirumoorthy <redacted> Add support for gpll0_out_aux clock which acts as the parent for the following networking subsystem (NSS) clocks. ce_clk cfg_clk eip_bfdcd_clk port1_rx_clk port1_tx_clk port2_tx_clk ppe_clk Acked-by: Konrad Dybcio <redacted> Signed-off-by: Kathiravan Thirumoorthy <redacted> Signed-off-by: Varadarajan Narayanan <redacted> --- v5: Update commit message --- drivers/clk/qcom/gcc-ipq5332.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c
index 9536b2b7d07c..c3020106dcf8 100644
--- a/drivers/clk/qcom/gcc-ipq5332.c
+++ b/drivers/clk/qcom/gcc-ipq5332.c@@ -89,6 +89,19 @@ static struct clk_alpha_pll_postdiv gpll0 = { }, }; +static struct clk_alpha_pll_postdiv gpll0_out_aux = { + .offset = 0x20000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "gpll0_out_aux", + .parent_hws = (const struct clk_hw *[]) { + &gpll0_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + static struct clk_alpha_pll gpll2_main = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS],
@@ -3442,6 +3455,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr, [GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr, [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr, + [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr, }; static const struct qcom_reset_map gcc_ipq5332_resets[] = {
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2.34.1