Thread (18 messages) 18 messages, 4 authors, 2024-10-22

[PATCH v5 1/8] dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock

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STALE729d REVIEWED: 1 (0M)

From: Varadarajan Narayanan <hidden>
Date: 2024-08-29 08:29:22
Also in: linux-arm-msm, linux-clk, linux-devicetree, linux-pm, lkml, netdev
Subsystem: arm/qualcomm mailing list, common clk framework, open firmware and flattened device tree bindings, qualcomm clock drivers, the rest · Maintainers: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Bjorn Andersson, Linus Torvalds

1 review trailer.

From: Kathiravan Thirumoorthy <redacted>

Add the definition for GPLL0_OUT_AUX clock. This acts as the parent
for the certain networking subsystem (NSS) clocks.

Acked-by: Krzysztof Kozlowski <redacted>
Signed-off-by: Kathiravan Thirumoorthy <redacted>
Signed-off-by: Varadarajan Narayanan <redacted>
---
v5: Update commit message to include why this clock is needed
---
 include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 +
 1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
index 8a405a0a96d0..24486eb47ed8 100644
--- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h
+++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h
@@ -179,6 +179,7 @@
 #define GCC_PCIE3X1_0_PIPE_CLK_SRC			170
 #define GCC_PCIE3X1_1_PIPE_CLK_SRC			171
 #define GCC_USB0_PIPE_CLK_SRC				172
+#define GPLL0_OUT_AUX					173
 
 #define GCC_ADSS_BCR					0
 #define GCC_ADSS_PWM_CLK_ARES				1
-- 
2.34.1

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