[PATCH 1/7] dt-bindings: arm: coresight-tmc: Add "memory-region" property
From: Linu Cherian <hidden>
Date: 2023-09-29 13:38:32
Also in:
linux-devicetree, lkml
Subsystem:
arm/coresight framework and drivers, open firmware and flattened device tree bindings, the rest · Maintainers:
Suzuki K Poulose, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Linus Torvalds
memory-region 0: Reserved trace buffer memory TMC ETR: When available, use this reserved memory region for trace data capture. Same region is used for trace data retention after a panic or watchdog reset. TMC ETF: When available, use this reserved memory region for trace data retention synced from internal SRAM after a panic or watchdog reset. memory-region 1: Reserved meta data memory TMC ETR, ETF: When available, use this memory for register snapshot retention synced from hardware registers after a panic or watchdog reset. Signed-off-by: Linu Cherian <redacted> --- .../bindings/arm/arm,coresight-tmc.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
index cb8dceaca70e..45ca4d02d73e 100644
--- a/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml@@ -101,6 +101,22 @@ properties: and ETF configurations. $ref: /schemas/graph.yaml#/properties/port + memory-region: + items: + - description: Reserved trace buffer memory for ETR and ETF sinks. + For ETR, this reserved memory region is used for trace data capture. + Same region is used for trace data retention as well after a panic + or watchdog reset. + For ETF, this reserved memory region is used for retention of trace + data synced from internal SRAM after a panic or watchdog reset. + + - description: Reserved meta data memory. Used for ETR and ETF sinks. + + memory-region-names: + items: + - const: trace-mem + - const: metadata-mem + required: - compatible - reg
@@ -115,6 +131,9 @@ examples: etr@20070000 { compatible = "arm,coresight-tmc", "arm,primecell"; reg = <0x20070000 0x1000>; + memory-region = <&etr_trace_mem_reserved>, + <&etr_mdata_mem_reserved>; + memory-region-names = "trace-mem", "metadata-mem"; clocks = <&oscclk6a>; clock-names = "apb_pclk";
--
2.34.1
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