Re: [PATCH 02/13] dt-bindings: memory: snps: Add Baikal-T1 DDRC support
From: Rob Herring <robh@kernel.org>
Date: 2022-08-30 18:01:23
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On Mon, Aug 22, 2022 at 10:19:45PM +0300, Serge Semin wrote:
Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There are individual IRQs for each ECC and DFI events.The dedicated scrubber clock source is absent since it's fully synchronous to the core clock. In addition to that the DFI-DDR PHY CSRs can be accessed via a separate registers space.
Are you sure the phy and dfi irq shouldn't be a separate device? Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel