[PATCH 02/13] dt-bindings: memory: snps: Add Baikal-T1 DDRC support
From: Serge Semin <hidden>
Date: 2022-08-22 19:21:48
Also in:
linux-devicetree, linux-edac, lkml
Subsystem:
arm/zynq architecture, memory controller drivers, open firmware and flattened device tree bindings, the rest · Maintainers:
Michal Simek, Krzysztof Kozlowski, Rob Herring, Conor Dooley, Linus Torvalds
Baikal-T1 DDR controller is based on the DW uMCTL2 DDRC IP-core v2.51a with up to DDR3 protocol capability and 32-bit data bus + 8-bit ECC. There are individual IRQs for each ECC and DFI events.The dedicated scrubber clock source is absent since it's fully synchronous to the core clock. In addition to that the DFI-DDR PHY CSRs can be accessed via a separate registers space. Signed-off-by: Serge Semin <redacted> --- .../memory-controllers/snps,dw-umctl2-ddrc.yaml | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
index 8db92210cfe1..899a6c5f9806 100644
--- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml@@ -26,6 +26,7 @@ properties: enum: - snps,ddrc-3.80a - xlnx,zynqmp-ddrc-2.40a + - baikal,bt1-ddrc interrupts: description:
@@ -49,7 +50,14 @@ properties: enum: [ ecc_ce, ecc_ue, ecc_ap, ecc_sbr, dfi_e ] reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + items: + - const: umctl2 + - const: phy clocks: description:
--
2.35.1
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