On 14/07/2022 17:00, Sudeep Holla wrote:

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On Thu, Jul 14, 2022 at 03:27:09PM +0000, Conor.Dooley@microchip.com wrote:

quoted

On 14/07/2022 16:01, Sudeep Holla wrote:

quoted

Interesting, need to check if it is not in atomic context on arm64.
Wonder if some configs are disabled and making this bug hidden. Let me
check.

OK, it turns I didn't have necessary config options enabled. Enabling
them, I did see the BUG splat and changing allocation to GFP_ATOMIC
fixed the same. Can you try that please so that you can test if other
things are fine.

quoted

quoted

One possible solution is to add GFP_ATOMIC to the allocation but I want
to make sure if it is legal to be in atomic context when calling
update_siblings_masks.

So I take is as legal and needs to be fixed to push my patch.

With the GFP_ATOMIC, behaviour is the same as before for me.

Therefore, with the following diff & for RISC-V/DT:

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index 65d566ff24c4..4b5cd08c5a65 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c

@@ -356,7 +356,7 @@ int detect_cache_attributes(unsigned int cpu)
                return -ENOENT;
 
        per_cpu_cacheinfo(cpu) = kcalloc(cache_leaves(cpu),
-                                        sizeof(struct cacheinfo), GFP_KERNEL);
+                                        sizeof(struct cacheinfo), GFP_ATOMIC);
        if (per_cpu_cacheinfo(cpu) == NULL) {
                cache_leaves(cpu) = 0;
                return -ENOMEM;

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