Re: [PATCH v5 09/19] arch_topology: Use the last level cache information from the cacheinfo

On Wed, Jun 29, 2022 at 06:18:25PM +0000, Conor.Dooley@microchip.com wrote:

On 29/06/2022 18:49, Conor.Dooley@microchip.com wrote:

quoted

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On 27/06/2022 17:50, Sudeep Holla wrote:

quoted

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The cacheinfo is now initialised early along with the CPU topology
initialisation. Instead of relying on the LLC ID information parsed
separately only with ACPI PPTT elsewhere, migrate to use the similar
information from the cacheinfo.

This is generic for both DT and ACPI systems. The ACPI LLC ID information
parsed separately can now be removed from arch specific code.

Hey Sudeep,
I bisected broken boot on PolarFire SoC to this patch in next-20220629 :/
I suspect the issue is a missing "next-level-cache" in the the dt:
arch/riscv/boot/dts/microchip/mpfs.dtsi

Adding next-level-cache = <&cctrllr> fixes the boot.

If the above is missing, even the existing cacheinfo will be incorrect on
that system. But we must end up with L1 as LLC, I need to check if that
breaks the boot.

No, no it doesn't. Not sure what I was thinking there.
Prob tested that on the the last commit that bisect tested
rather than the one it pointed out the problem was with.

So can I assume the pointed commit is where the boot breaks ?

Either way, boot is broken in -next.

OK, that's bad. 

quoted

Not sure what the resolution here is, old devicetrees are meant to keep
booting, right?

Ideally yes. But with this, I assume the cacheinfo to userspace is also broken
on this platform and I guess that needs fixing which can happen with DT update
only.

--
Regards,
Sudeep

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