Re: [PATCH 17/17] arm64: dts: mediatek: add mt8365-evk board device-tree
From: Krzysztof Kozlowski <hidden>
Date: 2022-06-01 10:41:15
Also in:
dmaengine, linux-devicetree, linux-i2c, linux-iio, linux-mediatek, linux-mmc, linux-phy, linux-serial, linux-spi, linux-usb, linux-watchdog, lkml
On 31/05/2022 15:50, Fabien Parent wrote:
Add device-tree for the MT8365-EVK board. The MT8365 EVK board has the following IOs: * DPI <-> HDMI bridge and HDMI connector. * 2 audio jack * 1 USB Type-A Host port * 2 UART to USB port * 1 battery connector * 1 eMMC * 1 SD card * 2 camera connectors * 1 M.2 slot for connectivity * 1 DSI connector + touchscreen connector * RPI compatible header * 1 Ethernet port
Thank you for your patch. There is something to discuss/improve.
quoted hunk ↗ jump to hunk
Signed-off-by: Fabien Parent <redacted> --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 578 ++++++++++++++++++++ 2 files changed, 579 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dtsdiff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index c7d4636a2cb7..02a9f784358e 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile@@ -40,4 +40,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtbdiff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts new file mode 100644 index 000000000000..8f472caa06a3 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts@@ -0,0 +1,578 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021 BayLibre, SAS. + * Author: Fabien Parent <fparent@baylibre.com> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/pinctrl/mt8365-pinfunc.h> +#include "mt8365.dtsi" +#include "mt6357.dtsi" + +/ { + model = "MediaTek MT8365 Open Platform EVK"; + compatible = "mediatek,mt8365-evk", "mediatek,mt8365"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + connector { + compatible = "hdmi-connector"; + label = "hdmi"; + type = "a"; + + port { + hdmi_connector_in: endpoint { + remote-endpoint = <&hdmi_connector_out>; + }; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + volume-up {
key-volume-up, volume-up-key or key-0
+ gpios = <&pio 24 GPIO_ACTIVE_LOW>;
+ label = "volume_up";
+ linux,code = <KEY_VOLUMEUP>;
+ wakeup-source;
+ debounce-interval = <15>;
+ };
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0xc0000000>;
+ };
+
+ usb_otg_vbus: regulator-2 {
+ compatible = "regulator-fixed";
+ regulator-name = "otg_vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 12 MiB reserved for OP-TEE (BL32)
+ * +-----------------------+ 0x43e0_0000
+ * | SHMEM 2MiB |
+ * +-----------------------+ 0x43c0_0000
+ * | | TA_RAM 8MiB |
+ * + TZDRAM +--------------+ 0x4340_0000
+ * | | TEE_RAM 2MiB |
+ * +-----------------------+ 0x4320_0000
+ */
+ optee_reserved: optee@43200000 {
+ no-map;
+ reg = <0 0x43200000 0 0x00c00000>;
+ };
+ };
+};
+
+&cpu0 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu1 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu2 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&cpu3 {
+ proc-supply = <&mt6357_vproc_reg>;
+ sram-supply = <&mt6357_vsram_proc_reg>;
+};
+
+&dpi0 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&dpi_func_pins>;
+ pinctrl-1 = <&dpi_idle_pins>;
+ assigned-clocks = <&topckgen CLK_TOP_DPI0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_LVDSPLL_D4>;
+
+ /*
+ * Ethernet and HDMI are sharing pins.
+ * Only one can be enabled at a time and require the physical switch
+ * SW2101 to be set on DPI position
+ */
+ status = "okay";
+
+ port {
+ dpi_out: endpoint {
+ remote-endpoint = <&it66121_in>;
+ };
+ };
+};
+
+ðernet {
+ pinctrl-names = "default";
+ pinctrl-0 = <ðernet_pins>;
+ phy-handle = <ð_phy>;
+ phy-mode = "rmii";
+ mac-address = [00 00 00 00 00 00];
+
+ /*
+ * Ethernet and HDMI are sharing pins.
+ * Only one can be enabled at a time and require the physical switch
+ * SW2101 to be set on LAN position
+ */
+ status = "disabled";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <100000>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;You defined address/size in DTSI.
+
+ it66121hdmitx: hdmi@4c {
+ compatible = "ite,it66121";
+ pinctrl-names = "default";
+ pinctrl-0 = <&ite_pins>;
+ vcn33-supply = <&mt6357_vibr_reg>;
+ vcn18-supply = <&mt6357_vsim2_reg>;
+ vrf12-supply = <&mt6357_vrf12_reg>;
+ reset-gpios = <&pio 69 GPIO_ACTIVE_LOW>;
+ interrupts-extended = <&pio 68 IRQ_TYPE_LEVEL_LOW>;
+ #sound-dai-cells = <0>;
+ reg = <0x4c>;Put reg after compatible.
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ it66121_in: endpoint {
+ bus-width = <12>;
+ remote-endpoint = <&dpi_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_connector_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+};
+
+&mmc0 {
+ status = "okay";Status okay goes to the end. In some nodes you keep that style, in some not. Confusing.
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc0_pins_default>;
+ pinctrl-1 = <&mmc0_pins_uhs>;
+ bus-width = <8>;
+ max-frequency = <200000000>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ cap-mmc-hw-reset;
+ no-sdio;
+ no-sd;
+ hs400-ds-delay = <0x12012>;
+ vmmc-supply = <&mt6357_vemc_reg>;
+ vqmmc-supply = <&mt6357_vio18_reg>;
+ assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL>;
+ non-removable;
+};
+
+&mmc1 {
+ pinctrl-names = "default", "state_uhs";
+ pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_uhs>;
+ cd-gpios = <&pio 76 GPIO_ACTIVE_LOW>;
+ bus-width = <4>;
+ max-frequency = <200000000>;
+ cap-sd-highspeed;
+ sd-uhs-sdr50;
+ sd-uhs-sdr104;
+ vmmc-supply = <&mt6357_vmch_reg>;
+ vqmmc-supply = <&mt6357_vio18_reg>;
+ status = "okay";
+};
+
+&mt6357_pmic {
+ interrupt-parent = <&pio>;
+ interrupts = <145 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+};
+
+&mt6357_vibr_reg {
+ regulator-always-on;
+};
+
+/* Needed by MSDC1 */
+&mt6357_vmc_reg {
+ regulator-always-on;
+};
+
+&mt6357_vrf12_reg {
+ regulator-always-on;
+};
+
+&mt6357_vsim2_reg {
+ regulator-always-on;
+};
+
+&mt6357keys {
+ power-key {
+ label = "power";
+ linux,keycodes = <KEY_POWER>;
+ wakeup-source;
+ };
+
+ volume-down {volume-down-key
+ label = "volume_down"; + linux,keycodes = <KEY_VOLUMEDOWN>;
Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel