[PATCH V4 2/5] dt-bindings: clock: Document MA35D1 clock controller bindings

@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/nuvoton,ma35d1-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 Clock Control Module Binding
+
+maintainers:
+  - Chi-Fang Li <cfli0@nuvoton.com>
+  - Jacky Huang <ychuang3@nuvoton.com>
+
+description: |
+  The MA35D1 clock controller generates clocks for the whole chip,
+  including system clocks and all peripheral clocks.
+
+  See also:
+    include/dt-bindings/clock/ma35d1-clk.h
+
+properties:
+  compatible:
+    const: nuvoton,ma35d1-clk
+
+  reg:
+    maxItems: 1
+
+  "#clock-cells":
+    const: 1
+
+  clocks:
+    items:
+      - description: External 24MHz crystal
+
+  clock-names:
+    items:
+      - const: hxt_24m
+
+  assigned-clocks:
+    maxItems: 5
+
+  assigned-clock-rates:
+    maxItems: 5
+
+  nuvoton,clk-pll-mode:
+    description:
+      A list of PLL operation mode corresponding to CAPLL, DDRPLL, APLL,
+      EPLL, and VPLL in sequential. The operation mode value 0 is for
+      integer mode, 1 is for fractional mode, and 2 is for spread
+      spectrum mode.
+    $ref: /schemas/types.yaml#/definitions/uint32-array
+    maxItems: 5
+    items:
+      minimum: 0
+      maximum: 2
+
+required:
+  - compatible
+  - reg
+  - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+
+    clk: clock-controller@40460200 {
+        compatible = "nuvoton,ma35d1-clk";
+        reg = <0x0 0x40460200 0x0 0x100>;
+        #clock-cells = <1>;
+        clocks = <&hxt_24m>;
+        clock-names = "HXT_24MHz";
+    };
+...