On Thu, Apr 21, 2022 at 4:44 PM Catalin Marinas [off-list ref] wrote:

On Thu, Apr 21, 2022 at 03:47:30PM +0200, Arnd Bergmann wrote:

quoted

On Thu, Apr 21, 2022 at 3:25 PM Catalin Marinas [off-list ref] wrote:

quoted

On Thu, Apr 21, 2022 at 02:28:45PM +0200, Arnd Bergmann wrote:

quoted

We also know that larger slabs are all cacheline aligned, so simply
comparing the transfer size is enough to rule out most, in this case
any transfer larger than 96 bytes must come from the kmalloc-128
or larger cache, so that works like before.

There's also the case with 128-byte cache lines and kmalloc-192.

Sure, but that's much less common, as the few machines with 128 byte
cache lines tend to also have cache coherent devices IIRC, so we'd
skip the bounce buffer entirely.

Do you know which machines still have 128-byte cache lines _and_
non-coherent DMA? If there isn't any that matters, I'd reduce
ARCH_DMA_MINALIGN to 64 now (while trying to get to even smaller kmalloc
caches).

I think the last time this came up, someone pointed out one of the
Qualcomm Snapdragon phone chips with their custom cores.

        Arnd

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