Re: [PATCH 07/10] crypto: Use ARCH_DMA_MINALIGN instead of ARCH_KMALLOC_MINALIGN
From: Catalin Marinas <catalin.marinas@arm.com>
Date: 2022-04-21 14:44:28
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On Thu, Apr 21, 2022 at 03:47:30PM +0200, Arnd Bergmann wrote:
On Thu, Apr 21, 2022 at 3:25 PM Catalin Marinas [off-list ref] wrote:quoted
On Thu, Apr 21, 2022 at 02:28:45PM +0200, Arnd Bergmann wrote:quoted
We also know that larger slabs are all cacheline aligned, so simply comparing the transfer size is enough to rule out most, in this case any transfer larger than 96 bytes must come from the kmalloc-128 or larger cache, so that works like before.There's also the case with 128-byte cache lines and kmalloc-192.Sure, but that's much less common, as the few machines with 128 byte cache lines tend to also have cache coherent devices IIRC, so we'd skip the bounce buffer entirely.
Do you know which machines still have 128-byte cache lines _and_ non-coherent DMA? If there isn't any that matters, I'd reduce ARCH_DMA_MINALIGN to 64 now (while trying to get to even smaller kmalloc caches).
quoted
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For transfers <=96 bytes, the possibilities are: 1.kmalloc-32 or smaller, always needs to bounce 2. kmalloc-96, but at least one byte in partial cache line, need to bounce 3. kmalloc-64, may skip the bounce. 4. kmalloc-128 or larger, or not a slab cache but a partial transfer, may skip the bounce. I would guess that the first case is the most common here, so unless bouncing one or two cache lines is extremely expensive, I don't expect it to be worth optimizing for the latter two cases.I think so. If someone complains of a performance regression, we can look at optimising the bounce. I have a suspicion the cost of copying two cache lines is small compared to swiotlb_find_slots() etc.That is possible, and we'd definitely have to watch out for performance regressions, I'm just skeptical that the cases that suffer from the extra bouncer buffering on 33..64 byte allocations benefit much from having a special case if the 1...32 and 65..96 byte allocations are still slow. Another simpler way to do this might be to just not create the kmalloc-96 (or kmalloc-192) caches, and assuming that any transfer >=33 (or 65) bytes is safe.
I'll give the dma bounce idea a go next week, see how it looks. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel