On Mon, 2022-03-21 at 17:30 -0500, Rob Herring wrote:

On Thu, Mar 17, 2022 at 10:39:24PM +0800, Moudy Ho wrote:

quoted

In order to allow modules with latency requirements such as MDP3
to set registers through CMDQ, add the relevant GCE property.

Signed-off-by: Moudy Ho <redacted>
Reviewed-by: AngeloGioacchino Del Regno <
angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <redacted>
---
 .../devicetree/bindings/soc/mediatek/mediatek,mutex.yaml  | 8
++++++++
 1 file changed, 8 insertions(+)

diff --git
a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yam
l
b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yam
l
index f825af49f820..a4892979480c 100644
---
a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yam
l
+++
b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yam
l

@@ -60,6 +60,14 @@ properties:
       include/dt-bindings/gce/<chip>-gce.h of each chips.
     $ref: /schemas/types.yaml#/definitions/phandle-array
 
+  mediatek,gce-client-reg:
+    description: The register of client driver can be configured

by gce with
+      4 arguments defined in this property, such as phandle of
gce, subsys id,
+      register offset and size. Each GCE subsys id is mapping to a
client
+      defined in the header include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1

items:
  items:
    - description: phandle of GCE
    - description: GCE subsys id
    - description: register offset
    - description: register size

Hi Rob,

Thanks for the review, I will follow the suggestions to make
corresponding corrections in the next version. Also, I'm sorry that I
left out the information about the dependent series that may cause YAML
checking fail.
ref: 
https://patchwork.kernel.org/project/linux-mediatek/list/?series=621899

Thanks,
Moudy

quoted

+
 required:
   - compatible
   - reg
-- 
2.18.0

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