@@ -80,6 +80,15 @@
 #define MT8183_MUTEX_MOD_DISP_GAMMA0		16
 #define MT8183_MUTEX_MOD_DISP_DITHER0		17
 
+#define MT8183_MUTEX_MOD_MDP_RDMA0		2
+#define MT8183_MUTEX_MOD_MDP_RSZ0		4
+#define MT8183_MUTEX_MOD_MDP_RSZ1		5
+#define MT8183_MUTEX_MOD_MDP_TDSHP0		6
+#define MT8183_MUTEX_MOD_MDP_WROT0		7
+#define MT8183_MUTEX_MOD_MDP_WDMA		8
+#define MT8183_MUTEX_MOD_MDP_AAL0		23
+#define MT8183_MUTEX_MOD_MDP_CCORR0		24
+
 #define MT8173_MUTEX_MOD_DISP_OVL0		11
 #define MT8173_MUTEX_MOD_DISP_OVL1		12
 #define MT8173_MUTEX_MOD_DISP_RDMA0		13

@@ -249,6 +258,33 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
 };
 
+static const struct mtk_mutex_mod mt8183_mutex_table_mod[MUTEX_TABLE_IDX_MAX] = {
+	[MUTEX_TABLE_IDX_MDP_RDMA0] = {
+		0, MT8183_MUTEX_MOD_MDP_RDMA0
+	},
+	[MUTEX_TABLE_IDX_MDP_RSZ0] = {
+		0, MT8183_MUTEX_MOD_MDP_RSZ0
+	},
+	[MUTEX_TABLE_IDX_MDP_RSZ1] = {
+		0, MT8183_MUTEX_MOD_MDP_RSZ1
+	},
+	[MUTEX_TABLE_IDX_MDP_TDSHP0] = {
+		0, MT8183_MUTEX_MOD_MDP_TDSHP0
+	},
+	[MUTEX_TABLE_IDX_MDP_WROT0] = {
+		0, MT8183_MUTEX_MOD_MDP_WROT0
+	},
+	[MUTEX_TABLE_IDX_MDP_WDMA] = {
+		0, MT8183_MUTEX_MOD_MDP_WDMA
+	},
+	[MUTEX_TABLE_IDX_MDP_AAL0] = {
+		0, MT8183_MUTEX_MOD_MDP_AAL0
+	},
+	[MUTEX_TABLE_IDX_MDP_CCORR0] = {
+		0, MT8183_MUTEX_MOD_MDP_CCORR0
+	},
+};
+
 static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,

@@ -340,6 +376,7 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
 	.mutex_sof = mt8183_mutex_sof,
 	.mutex_mod_reg = MT8183_MUTEX0_MOD0,
 	.mutex_sof_reg = MT8183_MUTEX0_SOF0,
+	.mutex_table_mod = mt8183_mutex_table_mod,
 	.no_clk = true,
 };