On Samstag, 27. November 2021 16:29:33 CET Johan Jonker wrote:

On 11/27/21 3:19 PM, Nicolas Frattaroli wrote:

quoted

The Quartz64 Model A has the SPI pins broken out on its pin
header. The actual pins being used though are not the m0
variant, but the m1 variant, which also lacks the cs1 pin.

This commit overrides pinctrl-0 accordingly for this board.

spi1 is intentionally left disabled, as anyone wishing to add
SPI devices needs to edit the dts anyway, and the pins are more
useful as GPIOs for the rest of the users.

Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
---
 arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 4d4b2a301b1a..166399b7f13f 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts

@@ -509,6 +509,11 @@ &spdif {
 	status = "okay";
 };
 
+&spi1 {

quoted

+	pinctrl-names = "default";

With the removal off pinctrl-1 the pinctrl-names property is already
correctly defined.

If it ever gets re-added in the future, it no longer is, so it's better
to be explicit right now than to risk one board breaking in the future
when the SoC's definition changes.

Regards,
Nicolas Frattaroli





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