Re: [PATCH v2 3/3] arm64: dts: rockchip: Add spi1 pins on Quartz64 A
From: Johan Jonker <hidden>
Date: 2021-11-27 15:31:40
Also in:
linux-devicetree, linux-rockchip, lkml
On 11/27/21 3:19 PM, Nicolas Frattaroli wrote:
quoted hunk ↗ jump to hunk
The Quartz64 Model A has the SPI pins broken out on its pin header. The actual pins being used though are not the m0 variant, but the m1 variant, which also lacks the cs1 pin. This commit overrides pinctrl-0 accordingly for this board. spi1 is intentionally left disabled, as anyone wishing to add SPI devices needs to edit the dts anyway, and the pins are more useful as GPIOs for the rest of the users. Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com> --- arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts | 5 +++++ 1 file changed, 5 insertions(+)diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts index 4d4b2a301b1a..166399b7f13f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts@@ -509,6 +509,11 @@ &spdif { status = "okay"; }; +&spi1 {
+ pinctrl-names = "default";
With the removal off pinctrl-1 the pinctrl-names property is already
correctly defined.
+ spi1: spi@fe620000 {
+ compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
+ reg = <0x0 0xfe620000 0x0 0x1000>;
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
+ clock-names = "spiclk", "apb_pclk";
+ dmas = <&dmac0 22>, <&dmac0 23>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
+};
+
&tsadc {
/* tshut mode 0:CRU 1:GPIO */
rockchip,hw-tshut-mode = <1>;_______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel