-----Original Message-----
From: Lucas Stach <l.stach@pengutronix.de>
Sent: Saturday, October 16, 2021 3:04 AM
To: Richard Zhu <hongxing.zhu@nxp.com>; tharvey@gateworks.com;
kishon@ti.com; vkoul@kernel.org; robh@kernel.org;
galak@kernel.crashing.org; shawnguo@kernel.org
Cc: linux-phy@lists.infradead.org; devicetree@vger.kernel.org;
linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
kernel@pengutronix.de; dl-linux-imx [off-list ref]
Subject: Re: [PATCH v3 8/9] arm64: dts: imx8mm-evk: add the pcie support on
imx8mm evk board

Am Dienstag, dem 12.10.2021 um 16:41 +0800 schrieb Richard Zhu:

quoted

Add the PCIe support on i.MX8MM EVK board.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi | 46
+++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi

b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 2d0684ac82f6..5ce43daa0c8b 100644

--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi

@@ -31,6 +31,23 @@ status {
 		};
 	};

+	pcie0_refclk: pcie0-refclk {
+		compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <100000000>;
+	};

This is both the PHY reference and bus clock. I guess you could just squash
Patch 4/9 into this one, as they are both required to get PCIe on the EVK
board.

[Richard Zhu] Okay, agree with that. Would squash #4 with #8 together.
Thanks.

quoted

+
+	reg_pcie0_gpio: regulator-pcie-gpio {

Drop the gpio suffix.

[Richard Zhu] Okay, would be dropped.

quoted

+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pcie0_reg>;
+		regulator-name = "MPCIE_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
 	reg_usdhc2_vmmc: regulator-usdhc2 {
 		compatible = "regulator-fixed";
 		pinctrl-names = "default";

@@ -296,6 +313,22 @@ &pcie_phy {
 	status = "okay";
 };

+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_pcie0>;
+	reset-gpio = <&gpio4 21 GPIO_ACTIVE_LOW>;
+	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>, <&clk

IMX8MM_CLK_PCIE1_AUX>,

quoted

+		 <&clk IMX8MM_CLK_DUMMY>, <&pcie0_refclk>;

The i.MX8MM PCIe driver should not request the pcie_phy clock. Please add
a change in the driver, so we don't need to hook up a useless dummy clock to
this node.

[Richard Zhu] Okay, thanks.

Regards,
Lucas

quoted

+	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
+	assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>,
+			  <&clk IMX8MM_CLK_PCIE1_CTRL>;
+	assigned-clock-rates = <10000000>, <250000000>;
+	assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>,
+				 <&clk IMX8MM_SYS_PLL2_250M>;
+	vpcie-supply = <&reg_pcie0_gpio>;
+	status = "okay";
+};
+
 &sai3 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_sai3>;

@@ -413,6 +446,19 @@ MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA

	0x400001c3

quoted

 		>;
 	};

+	pinctrl_pcie0: pcie0grp {
+		fsl,pins = <
+			MX8MM_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B    0x61
+			MX8MM_IOMUXC_SAI2_RXFS_GPIO4_IO21       0x41
+		>;
+	};
+
+	pinctrl_pcie0_reg: pcie0reggrp {
+		fsl,pins = <
+			MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5       0x41
+		>;
+	};
+
 	pinctrl_pmic: pmicirqgrp {
 		fsl,pins = <
 			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x141

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