RE: [PATCH 3/9] ARM: dts: renesas: Add compatible properties to KSZ9031 Ethernet PHYs

-----Original Message-----
From: Geert Uytterhoeven <geert+renesas@glider.be>
Sent: 09 September 2021 09:50
To: Magnus Damm <magnus.damm@gmail.com>
Cc: Biju Das <biju.das.jz@bp.renesas.com>; Adam Ford <redacted>;
Florian Fainelli [off-list ref]; Andrew Lunn [off-list ref];
Heiner Kallweit [off-list ref]; Russell King
[off-list ref]; Grygorii Strashko [off-list ref];
linux-renesas-soc@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
netdev@vger.kernel.org; devicetree@vger.kernel.org; Geert Uytterhoeven
[off-list ref]
Subject: [PATCH 3/9] ARM: dts: renesas: Add compatible properties to
KSZ9031 Ethernet PHYs

Add compatible values to Ethernet PHY subnodes representing Micrel
KSZ9031 PHYs on RZ/G1 boards. This allows software to identify the PHY
model at any time, regardless of the state of the PHY reset line.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
I could not verify the PHY revision number (least significant nibble of
the ID), due to lack of hardware.
---
 arch/arm/boot/dts/iwg20d-q7-common.dtsi     | 2 ++
 arch/arm/boot/dts/r8a7742-iwg21d-q7.dts     | 2 ++
 arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 2 ++
 arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts   | 2 ++
 4 files changed, 8 insertions(+)

diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi

b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
index bc857676d19104a1..849034a49a3f98e2 100644

--- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
+++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi

@@ -158,6 +158,8 @@ &avb {
 	status = "okay";

 	phy3: ethernet-phy@3 {
+		compatible = "ethernet-phy-id0022.1622",
+			     "ethernet-phy-ieee802.3-c22";
 		reg = <3>;
 		micrel,led-mode = <1>;
 	};

diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts

b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
index 94bf8a116b5242a9..a5a79cdbcd0ee09b 100644

--- a/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts
+++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7.dts

@@ -175,6 +175,8 @@ &avb {
 	status = "okay";

 	phy3: ethernet-phy@3 {
+		compatible = "ethernet-phy-id0022.1622",
+			     "ethernet-phy-ieee802.3-c22";
 		reg = <3>;
 		micrel,led-mode = <1>;
 	};

diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts

b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index 73bd62d8a929e5da..c105932f642ea517 100644

--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts

@@ -123,6 +123,8 @@ phy3: ethernet-phy@3 {
 	 * On some older versions of the platform (before R4.0) the phy

address
 	 * may be 1 or 3. The address is fixed to 3 for R4.0 onwards.
 	 */
+		compatible = "ethernet-phy-id0022.1622",
+			     "ethernet-phy-ieee802.3-c22";
 		reg = <3>;
 		micrel,led-mode = <1>;
 	};

diff --git a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts

b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
index 8ac61b50aec03190..b024621c998103b2 100644

--- a/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts
+++ b/arch/arm/boot/dts/r8a77470-iwg23s-sbc.dts

@@ -79,6 +79,8 @@ &avb {
 	status = "okay";

 	phy3: ethernet-phy@3 {
+		compatible = "ethernet-phy-id0022.1622",
+			     "ethernet-phy-ieee802.3-c22";
 		reg = <3>;
 		interrupt-parent = <&gpio5>;
 		interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
--

2.25.1