If we're lucky enough to have been booted into secure PL1, we can switch
to monitor mode with an exception return rather than an SMC call, which
avoids the need for boot-time vectors.
Note that while all Secure PL1 register state is accessible in Secure
SVC mode, we must switch to Monitor mode before we set SCR.NS=1.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
arch/aarch32/boot.S | 19 ++++---------------
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S
index 82927de..e397cb0 100644
--- a/arch/aarch32/boot.S
+++ b/arch/aarch32/boot.S
@@ -37,9 +37,10 @@ ASM_FUNC(_start)
b start_no_el3
_switch_monitor:
- ldr r0, =boot_vectors
- bl setup_vector
- smc #0
+ adr lr, _monitor
+ ldr r0, =(PSR_A | PSR_I | PSR_F | PSR_MON)
+ msr spsr, r0
+ movs pc, lr
_monitor:
/* Move the stack to Monitor mode*/
@@ -102,18 +103,6 @@ ASM_FUNC(jump_kernel)
msr spsr_cxf, r4
movs pc, lr
- .section .vectors
- .align 6
-boot_vectors:
- b .
- b .
- b _monitor
- b .
- b .
- b .
- b .
- b .
-
.section .data
.align 2
flag_no_el3:
--
2.11.0
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