From: Mark Rutland <mark.rutland@arm.com> Date: 2021-08-24 13:51:53
These are a few cleanup patches I've split out of my ongoing bootwrapper
rework, and intend to apply by the end of this week.
My WIP cleanup branch with subsequent patches can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git cleanup
Thanks,
Mark.
Mark Rutland (5):
Remove unused Set/Way cache helpers
aarch32: simplify _switch_monitor
GICv3: initialize without RMW
Rename kernel *_RESET values to *_KERNEL
Rename `CNTFRQ` -> `COUNTER_FREQ`
Makefile.am | 4 ++--
arch/aarch32/boot.S | 25 +++++++------------------
arch/aarch32/include/asm/cpu.h | 30 ++----------------------------
arch/aarch32/include/asm/gic-v3.h | 7 -------
arch/aarch64/boot.S | 6 +++---
arch/aarch64/include/asm/cpu.h | 32 +++-----------------------------
arch/aarch64/include/asm/gic-v3.h | 7 -------
common/gic-v3.c | 8 +++-----
8 files changed, 20 insertions(+), 99 deletions(-)
--
2.11.0
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From: Mark Rutland <mark.rutland@arm.com> Date: 2021-08-24 13:52:04
We removed the Set/Way cache maintenance in commit:
864182b26c20a39d ("Remove cache maintenance")
... but forgot to remove the arch helpers which are now unused.
Remove the unused helpers.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
arch/aarch32/include/asm/cpu.h | 26 --------------------------
arch/aarch64/include/asm/cpu.h | 26 --------------------------
2 files changed, 52 deletions(-)
From: Mark Rutland <mark.rutland@arm.com> Date: 2021-08-24 13:52:17
If we're lucky enough to have been booted into secure PL1, we can switch
to monitor mode with an exception return rather than an SMC call, which
avoids the need for boot-time vectors.
Note that while all Secure PL1 register state is accessible in Secure
SVC mode, we must switch to Monitor mode before we set SCR.NS=1.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
arch/aarch32/boot.S | 19 ++++---------------
1 file changed, 4 insertions(+), 15 deletions(-)
From: Mark Rutland <mark.rutland@arm.com> Date: 2021-08-24 13:52:20
There's no need to perform an RMW sequence to initialize ICC_SRE_EL3, as
there are no bits that we need to preserve, and generally we should
reset registers to specific values such that RESx bits aren't configured
to UNKNOWN values that could be problematic in future architecture
versions.
Instead, let's initialize ICC_SRE_EL3 with a constant value. Since the
`DIB` and `DFB` fields are RAO/WI in some configurations and we have no
reason to initialize these to 0, we always initialize these to 1, in
addition to `SRE` and `SRE_Enable`.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Alexandru Elisei <redacted>
Cc: Andre Przywara <andre.przywara@arm.com>
---
arch/aarch32/include/asm/gic-v3.h | 7 -------
arch/aarch64/include/asm/gic-v3.h | 7 -------
common/gic-v3.c | 8 +++-----
3 files changed, 3 insertions(+), 19 deletions(-)
From: Mark Rutland <mark.rutland@arm.com> Date: 2021-08-24 13:52:33
Our *_RESET constants are used to initalize state for the kernel rather
than the bootwrapper itself, so for clarity we should use a *_KERNEL
suffix rather than a _RESET suffix.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
arch/aarch32/boot.S | 4 ++--
arch/aarch32/include/asm/cpu.h | 4 ++--
arch/aarch64/boot.S | 4 ++--
arch/aarch64/include/asm/cpu.h | 6 +++---
4 files changed, 9 insertions(+), 9 deletions(-)
From: Mark Rutland <mark.rutland@arm.com> Date: 2021-08-24 13:53:04
To avoid any confusuion between the CNTFRQ/CNTFRQ_EL0 register and the
vallue it will be progrmamed with, rename the `CNTFRQ` constant to
`COUNTER_FREQ.
In future patches this will allow us to use `CNTFRQ` as a macro for the
AArch32 CP15 register encoding.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
Makefile.am | 4 ++--
arch/aarch32/boot.S | 2 +-
arch/aarch64/boot.S | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
From: Andre Przywara <andre.przywara@arm.com> Date: 2021-08-24 16:51:25
On 8/24/21 2:48 PM, Mark Rutland wrote:
We removed the Set/Way cache maintenance in commit:
864182b26c20a39d ("Remove cache maintenance")
... but forgot to remove the arch helpers which are now unused.
Remove the unused helpers.
Indeed, no users in the tree.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Thanks,
Andre
From: Andre Przywara <andre.przywara@arm.com> Date: 2021-08-24 16:51:51
On 8/24/21 2:48 PM, Mark Rutland wrote:
If we're lucky enough to have been booted into secure PL1, we can switch
to monitor mode with an exception return rather than an SMC call, which
avoids the need for boot-time vectors.
Note that while all Secure PL1 register state is accessible in Secure
SVC mode, we must switch to Monitor mode before we set SCR.NS=1.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
I don't know much about the subtle differences between smc, movs pc and
eret, but from what I read this is indeed an easier way to get to MON.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
From: Andre Przywara <andre.przywara@arm.com> Date: 2021-08-24 16:52:10
On 8/24/21 2:48 PM, Mark Rutland wrote:
There's no need to perform an RMW sequence to initialize ICC_SRE_EL3, as
there are no bits that we need to preserve, and generally we should
reset registers to specific values such that RESx bits aren't configured
to UNKNOWN values that could be problematic in future architecture
versions.
Instead, let's initialize ICC_SRE_EL3 with a constant value. Since the
`DIB` and `DFB` fields are RAO/WI in some configurations and we have no
reason to initialize these to 0, we always initialize these to 1, in
addition to `SRE` and `SRE_Enable`.
Indeed, actually the architectural reset value is 0 (bypass enabled),
and we seem to be just saved by the fact that the model implements them
as RAO/WI. So forcing a value is the right thing to do.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Alexandru Elisei <redacted>
Cc: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
From: Andre Przywara <andre.przywara@arm.com> Date: 2021-08-24 16:52:26
On 8/24/21 2:48 PM, Mark Rutland wrote:
Our *_RESET constants are used to initalize state for the kernel rather
than the bootwrapper itself, so for clarity we should use a *_KERNEL
suffix rather than a _RESET suffix.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
It's indeed only renaming:
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
From: Andre Przywara <andre.przywara@arm.com> Date: 2021-08-24 16:52:42
On 8/24/21 2:49 PM, Mark Rutland wrote:
To avoid any confusuion between the CNTFRQ/CNTFRQ_EL0 register and the
vallue it will be progrmamed with, rename the `CNTFRQ` constant to
`COUNTER_FREQ.
In future patches this will allow us to use `CNTFRQ` as a macro for the
AArch32 CP15 register encoding.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Confirmed to be just renaming:
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
From: Marc Zyngier <maz@kernel.org> Date: 2021-08-25 09:49:03
On Tue, 24 Aug 2021 14:48:55 +0100,
Mark Rutland [off-list ref] wrote:
These are a few cleanup patches I've split out of my ongoing bootwrapper
rework, and intend to apply by the end of this week.
My WIP cleanup branch with subsequent patches can be found at:
git://git.kernel.org/pub/scm/linux/kernel/git/mark/boot-wrapper-aarch64.git cleanup
Thanks,
Mark.
Mark Rutland (5):
Remove unused Set/Way cache helpers
aarch32: simplify _switch_monitor
GICv3: initialize without RMW
Rename kernel *_RESET values to *_KERNEL
Rename `CNTFRQ` -> `COUNTER_FREQ`
Makefile.am | 4 ++--
arch/aarch32/boot.S | 25 +++++++------------------
arch/aarch32/include/asm/cpu.h | 30 ++----------------------------
arch/aarch32/include/asm/gic-v3.h | 7 -------
arch/aarch64/boot.S | 6 +++---
arch/aarch64/include/asm/cpu.h | 32 +++-----------------------------
arch/aarch64/include/asm/gic-v3.h | 7 -------
common/gic-v3.c | 8 +++-----
8 files changed, 20 insertions(+), 99 deletions(-)
For the whole series:
Acked-by: Marc Zyngier <maz@kernel.org>
M.
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Without deviation from the norm, progress is not possible.
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