Hi Andreas
On Thu, 2021-08-12 at 19:42 +0200, Andreas Färber wrote:

Hi Chester et al.,

On 05.08.21 08:54, Chester Lin wrote:

quoted

Add serial/uart support for NXP S32G2.

You might mention here that (following our initial stub) this commit
is
now apparently based on the CodeAurora BSP branch foo (and therefore
adding its last-year copyright below and separate from 4/8).

quoted

@NXP: If there are downstream Signed-off-bys that you would like to
see
included for this portion here, please speak up.

Larisa signed-off should be added.
Signed-off-by: Larisa Grigore <redacted>

quoted

Signed-off-by: Chester Lin <redacted>
---
 arch/arm64/boot/dts/freescale/s32g2.dtsi | 31
++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi

b/arch/arm64/boot/dts/freescale/s32g2.dtsi
index 3321819c1a2d..0076eacad8a6 100644

--- a/arch/arm64/boot/dts/freescale/s32g2.dtsi
+++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi

@@ -1,6 +1,7 @@

 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
 /*
  * Copyright (c) 2021 SUSE LLC
+ * Copyright 2017-2020 NXP

@NXP: Should this be updated to include 2021 from your latest BSP
releases? Do you want it visually aligned by adding the ASCII-art?

Yes for both questions. The copyright year sould be updated to 2021 and
should be visually aligned.

quoted

  */
 
 #include <dt-bindings/interrupt-controller/arm-gic.h>

@@ -11,6 +12,12 @@ / {

        #address-cells = <2>;
        #size-cells = <2>;
 
+       aliases {
+               serial0 = &uart0;
+               serial1 = &uart1;
+               serial2 = &uart2;
+       };

Note: In the past there had been controversies as to whether to
define
aliases globally for a SoC or in a .dts specific to a board's usage.
In this case it does not seem to matter much, as uart0 is being used
as
console on the reference boards.

quoted

+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;

@@ -82,6 +89,30 @@ soc {

 
                ranges;
 
+               uart0: serial@401c8000 {
+                       compatible = "fsl,s32g2-linflexuart",
+                                    "fsl,s32v234-linflexuart";
+                       reg = <0 0x401c8000 0 0x3000>;
+                       interrupts = <GIC_SPI 82
IRQ_TYPE_EDGE_RISING>;
+                       status = "disabled";
+               };
+
+               uart1: serial@401cc000 {
+                       compatible = "fsl,s32g2-linflexuart",
+                                    "fsl,s32v234-linflexuart";
+                       reg = <0 0x401cc000 0 0x3000>;
+                       interrupts = <GIC_SPI 83
IRQ_TYPE_EDGE_RISING>;
+                       status = "disabled";
+               };
+
+               uart2: serial@402bc000 {
+                       compatible = "fsl,s32g2-linflexuart",
+                                    "fsl,s32v234-linflexuart";
+                       reg = <0 0x402bc000 0 0x3000>;
+                       interrupts = <GIC_SPI 84
IRQ_TYPE_EDGE_RISING>;
+                       status = "disabled";
+               };
+
                gic: interrupt-controller@50800000 {
                        compatible = "arm,gic-v3";
                        #interrupt-cells = <3>;

Regards,
Andreas

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