[PATCH 5/6] pwm: sun4i: shorten the delay to 2 cycles
From: Roman Beranek <hidden>
Date: 2021-05-31 04:49:01
Also in:
linux-pwm, linux-sunxi
Subsystem:
pwm subsystem, the rest · Maintainers:
Uwe Kleine-König, Linus Torvalds
As Emil Lenngren has previously shown, actually only 1-2 cycles of the prescaler-divided clock are necessary to pass before the PWM turns off (instead of a full period). I was able to reproduce his observation on a A64 using a logic analyzer. Suggested-by: Emil Lenngren <redacted> Suggested-by: Pascal Roeleven <redacted> Signed-off-by: Roman Beranek <redacted> --- drivers/pwm/pwm-sun4i.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index 8218173ce3f6..6ab06b9749d0 100644
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c@@ -71,7 +71,7 @@ static const u32 prescaler_table[] = { 72000, 0, 0, - 0, /* Actually 1 but tested separately */ + 1, /* Tested separately */ }; struct sun4i_pwm_data {
@@ -240,7 +240,7 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, struct pwm_state cstate; u32 ctrl, duty = 0, period = 0, val; int ret; - unsigned int prescaler = 0; + unsigned int cycle_ns, current_prescaler, prescaler = 0; bool bypass; pwm_get_state(pwm, &cstate);
@@ -277,7 +277,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); } - if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) { + current_prescaler = PWM_REG_PRESCAL(ctrl, pwm->hwpwm); + if (current_prescaler != prescaler) { /* Prescaler changed, the clock has to be gated */ ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
@@ -308,8 +309,10 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, return 0; } - /* We need a full period to elapse before disabling the channel. */ - fsleep(cstate.period / NSEC_PER_USEC + 1); + /* We need to wait 1-2 cycles before disabling the channel. */ + cycle_ns = DIV_ROUND_UP(NSEC_PER_SEC, clk_get_rate(sun4i_pwm->clk)) + * prescaler_table[current_prescaler]; + fsleep(DIV_ROUND_UP(cycle_ns * 2, NSEC_PER_USEC)); ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
--
2.31.1
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