Hi, Tony, Catalin

On Thu, Apr 29, 2021 at 05:50:20PM +0000, Luck, Tony wrote:

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[Sector cache function]
The sector cache function split cache into multiple sectors and
control them separately. It is implemented on the L1D cache and
L2 cache in the A64FX processor and can be controlled
individually for L1D cache and L2 cache. A64FX has no L3 cache.
Each L1D cache and
L2 cache has 4 sectors. Which L1D sector is used is specified by
the value of [57:56] bits of address, how many ways of sector are
specified by the value of register (IMP_SCCR_L1_EL0).
Which L2 sector is used is specified by the value of [56] bits of
address, and how many ways of sector are specified by value of
register (IMP_SCCR_ASSIGN_EL1, IMP_SCCR_SET0_L2_EL1,
IMP_SCCR_SET1_L2_EL1).

Are A64FX binaries position independent?  I.e. could the OS reassign a
running task to a different sector by remapping it to different
virtual addresses during a context switch?

Arm64 supports a maximum of 52-bit of virtual or physical addresses. The
maximum the MMU would produce would be a 52-bit output address. I
presume bits 56, 57 of the address bus are used for some cache affinity (sector
selection) but they don't influence the memory addressing, nor could the MMU
set them.

Yes, A64FX binaries are position independent. Arm64 supports 
a maximum of 52-bit of virtual or physical address. On A64FX, 
the [56:57] bits of virtual addresses are used for some cache 
affinity (sector selection) and set by user program instead of MMU.

Best regards,
Tan Shaopeng

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