quoted

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[Sector cache function]
The sector cache function split cache into multiple sectors and
control them separately. It is implemented on the L1D cache and
L2 cache in the A64FX processor and can be controlled individually
for L1D cache and L2 cache. A64FX has no L3 cache. Each L1D cache and
L2 cache has 4 sectors. Which L1D sector is used is specified by the
value of [57:56] bits of address, how many ways of sector are
specified by the value of register (IMP_SCCR_L1_EL0).
Which L2 sector is used is specified by the value of [56] bits of
address, and how many ways of sector are specified by value of
register (IMP_SCCR_ASSIGN_EL1, IMP_SCCR_SET0_L2_EL1,
IMP_SCCR_SET1_L2_EL1).

Are A64FX binaries position independent?  I.e. could the OS reassign
a running task to a different sector by remapping it to different virtual
addresses during a context switch?

Or is this a static property at task launch?

-Tony

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