[PATCH v5 0/2] Add L1 and L2 error detection for A53 and A57
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: 2021-04-01 11:08:04
Also in:
linux-edac
Hi, Resending this mainly because Marc Zyngier and Mark Rutland raised concerns about using implementation defined registers and I forgot to Cc them with the last version. This version, like v4 already, should fix these concerns. Looking forward to feedback. Sascha Changes since v4: - Rebase on v5.12-rc5 Changes since v3: - Add edac-enabled property to make EDAC support optional Changes since v2: - drop usage of virtual dt node (Robh) - use read_sysreg_s instead of open coded variant (James Morse) - separate error retrieving from error reporting - use smp_call_function_single rather than smp_call_function_single_async - make driver single instance and register all 'cpu' hierarchy up front once Changes since v1: - Split dt-binding into separate patch - Sort local function variables in reverse-xmas tree order - drop unnecessary comparison and make variable bool Sascha Hauer (2): drivers/edac: Add L1 and L2 error detection for A53 and A57 dt-bindings: arm: cpus: Add edac-enabled property .../devicetree/bindings/arm/cpus.yaml | 6 + drivers/edac/Kconfig | 6 + drivers/edac/Makefile | 1 + drivers/edac/cortex_arm64_l1_l2.c | 221 ++++++++++++++++++ 4 files changed, 234 insertions(+) create mode 100644 drivers/edac/cortex_arm64_l1_l2.c -- 2.29.2 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel