[PATCH iv4 0/2] Add L1 and L2 error detection for A53 and A57
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: 2021-02-01 12:01:33
Also in:
linux-edac
Hi All, As mentioned by Marc and Mark usage of the implementation defined registers is not generally safe, they can't be used in virtualized environments or when EL3 already uses the same registers. This is probably the last attempt to get this upstream, I added an additional property to the CPU device nodes to be set explicitly when using these registers is safe and desired. Sascha Changes since v3: - Add edac-enabled property to make EDAC support optional Changes since v2: - drop usage of virtual dt node (Robh) - use read_sysreg_s instead of open coded variant (James Morse) - separate error retrieving from error reporting - use smp_call_function_single rather than smp_call_function_single_async - make driver single instance and register all 'cpu' hierarchy up front once Changes since v1: - Split dt-binding into separate patch - Sort local function variables in reverse-xmas tree order - drop unnecessary comparison and make variable bool Sascha Hauer (2): drivers/edac: Add L1 and L2 error detection for A53 and A57 dt-bindings: arm: cpus: Add edac-enabled property .../devicetree/bindings/arm/cpus.yaml | 6 + drivers/edac/Kconfig | 6 + drivers/edac/Makefile | 1 + drivers/edac/cortex_arm64_l1_l2.c | 221 ++++++++++++++++++ 4 files changed, 234 insertions(+) create mode 100644 drivers/edac/cortex_arm64_l1_l2.c -- 2.20.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel