Re: [PATCH] arm64/mm: Fix __enable_mmu() for new TGRAN range values

On Mon, Mar 08, 2021 at 01:30:53PM +0000, Will Deacon wrote:

On Sun, Mar 07, 2021 at 05:24:21PM +0530, Anshuman Khandual wrote:

quoted

On 3/5/21 8:21 PM, Mark Rutland wrote:

quoted

On Fri, Mar 05, 2021 at 08:06:09PM +0530, Anshuman Khandual wrote:

quoted

quoted

quoted

+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT	0x0
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE	0x1
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN	0x2
+#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX	0x7

The TGRAN2 fields doesn't quite follow the usual ID scheme rules, so how
do we deteremine the max value? Does the ARM ARM say anything in
particular about them, like we do for some of the PMU ID fields?

Did not find anything in ARM ARM, regarding what scheme TGRAN2 fields
actually follow. I had arrived at more restrictive 0x7 value, like the
usual signed fields as the TGRAN4 fields definitely do not follow the
unsigned ID scheme. Would restricting max value to 0x3 (i.e LPA2) be a
better option instead ?

I don't think it helps much, as TGRAN64_2 doesn't even define 0x3.

So I think this patch is probably the best we can do, but the Arm ARM could
really do with describing the scheme here.

I agree, and I've filed a ticket internally to try to get this cleaned
up.

I suspect that the answer is that these are basically unsigned, with
0x2-0xf indicating presence, but I can't guarantee that.

Thanks,
Mark.

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