From: James Morse <james.morse@arm.com>
As per ARM ARM DDI 0487G.a, when FEAT_LPA2 is implemented, ID_AA64MMFR0_EL1
might contain a range of values to describe supported translation granules
(4K and 16K pages sizes in particular) instead of just enabled or disabled
values. This changes __enable_mmu() function to handle complete acceptable
range of values (depending on whether the field is signed or unsigned) now
represented with ID_AA64MMFR0_TGRAN_SUPPORTED_[MIN..MAX] pair. While here,
also fix similar situations in EFI stub and KVM as well.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-efi@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Anshuman Khandual <redacted>
---
arch/arm64/include/asm/sysreg.h | 20 ++++++++++++++------
arch/arm64/kernel/head.S | 6 ++++--
arch/arm64/kvm/reset.c | 23 ++++++++++++-----------
drivers/firmware/efi/libstub/arm64-stub.c | 2 +-
4 files changed, 31 insertions(+), 20 deletions(-)
@@ -300,27 +300,28 @@ int kvm_set_ipa_limit(void)switch(PAGE_SIZE){default:caseSZ_4K:-tgran_2=ID_AA64MMFR0_TGRAN4_2_SHIFT;+tgran_2_shift=ID_AA64MMFR0_TGRAN4_2_SHIFT;break;caseSZ_16K:-tgran_2=ID_AA64MMFR0_TGRAN16_2_SHIFT;+tgran_2_shift=ID_AA64MMFR0_TGRAN16_2_SHIFT;break;caseSZ_64K:-tgran_2=ID_AA64MMFR0_TGRAN64_2_SHIFT;+tgran_2_shift=ID_AA64MMFR0_TGRAN64_2_SHIFT;break;}-switch(cpuid_feature_extract_unsigned_field(mmfr0,tgran_2)){-default:-case1:+tgran_2=cpuid_feature_extract_unsigned_field(mmfr0,tgran_2_shift);+if(tgran_2==ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE){kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");return-EINVAL;-case0:+}elseif(tgran_2==ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT){kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n");-break;-case2:+}elseif(tgran_2>=ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN&&+tgran_2<=ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX){kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n");-break;+}else{+kvm_err("Unsupported value, giving up\n");+return-EINVAL;}kvm_ipa_limit=id_aa64mmfr0_parange_to_phys_shift(parange);
@@ -24,7 +24,7 @@ efi_status_t check_platform_features(void)returnEFI_SUCCESS;tg=(read_cpuid(ID_AA64MMFR0_EL1)>>ID_AA64MMFR0_TGRAN_SHIFT)&0xf;-if(tg!=ID_AA64MMFR0_TGRAN_SUPPORTED){+if(tg<ID_AA64MMFR0_TGRAN_SUPPORTED_MIN||tg>ID_AA64MMFR0_TGRAN_SUPPORTED_MAX){if(IS_ENABLED(CONFIG_ARM64_64K_PAGES))efi_err("This 64 KB granular kernel is not supported by your CPU\n");else
--
2.7.4
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From: Mark Rutland <mark.rutland@arm.com> Date: 2021-03-05 14:52:08
On Fri, Mar 05, 2021 at 08:06:09PM +0530, Anshuman Khandual wrote:
quoted hunk
From: James Morse <james.morse@arm.com>
As per ARM ARM DDI 0487G.a, when FEAT_LPA2 is implemented, ID_AA64MMFR0_EL1
might contain a range of values to describe supported translation granules
(4K and 16K pages sizes in particular) instead of just enabled or disabled
values. This changes __enable_mmu() function to handle complete acceptable
range of values (depending on whether the field is signed or unsigned) now
represented with ID_AA64MMFR0_TGRAN_SUPPORTED_[MIN..MAX] pair. While here,
also fix similar situations in EFI stub and KVM as well.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-efi@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Anshuman Khandual <redacted>
---
arch/arm64/include/asm/sysreg.h | 20 ++++++++++++++------
arch/arm64/kernel/head.S | 6 ++++--
arch/arm64/kvm/reset.c | 23 ++++++++++++-----------
drivers/firmware/efi/libstub/arm64-stub.c | 2 +-
4 files changed, 31 insertions(+), 20 deletions(-)
The TGRAN2 fields doesn't quite follow the usual ID scheme rules, so how
do we deteremine the max value? Does the ARM ARM say anything in
particular about them, like we do for some of the PMU ID fields?
Otherwise, this patch looks correct to me.
Thanks,
Mark.
@@ -300,27 +300,28 @@ int kvm_set_ipa_limit(void)switch(PAGE_SIZE){default:caseSZ_4K:-tgran_2=ID_AA64MMFR0_TGRAN4_2_SHIFT;+tgran_2_shift=ID_AA64MMFR0_TGRAN4_2_SHIFT;break;caseSZ_16K:-tgran_2=ID_AA64MMFR0_TGRAN16_2_SHIFT;+tgran_2_shift=ID_AA64MMFR0_TGRAN16_2_SHIFT;break;caseSZ_64K:-tgran_2=ID_AA64MMFR0_TGRAN64_2_SHIFT;+tgran_2_shift=ID_AA64MMFR0_TGRAN64_2_SHIFT;break;}-switch(cpuid_feature_extract_unsigned_field(mmfr0,tgran_2)){-default:-case1:+tgran_2=cpuid_feature_extract_unsigned_field(mmfr0,tgran_2_shift);+if(tgran_2==ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE){kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");return-EINVAL;-case0:+}elseif(tgran_2==ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT){kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n");-break;-case2:+}elseif(tgran_2>=ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN&&+tgran_2<=ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX){kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n");-break;+}else{+kvm_err("Unsupported value, giving up\n");+return-EINVAL;}kvm_ipa_limit=id_aa64mmfr0_parange_to_phys_shift(parange);
@@ -24,7 +24,7 @@ efi_status_t check_platform_features(void)returnEFI_SUCCESS;tg=(read_cpuid(ID_AA64MMFR0_EL1)>>ID_AA64MMFR0_TGRAN_SHIFT)&0xf;-if(tg!=ID_AA64MMFR0_TGRAN_SUPPORTED){+if(tg<ID_AA64MMFR0_TGRAN_SUPPORTED_MIN||tg>ID_AA64MMFR0_TGRAN_SUPPORTED_MAX){if(IS_ENABLED(CONFIG_ARM64_64K_PAGES))efi_err("This 64 KB granular kernel is not supported by your CPU\n");else
On Fri, Mar 05, 2021 at 08:06:09PM +0530, Anshuman Khandual wrote:
quoted
From: James Morse <james.morse@arm.com>
As per ARM ARM DDI 0487G.a, when FEAT_LPA2 is implemented, ID_AA64MMFR0_EL1
might contain a range of values to describe supported translation granules
(4K and 16K pages sizes in particular) instead of just enabled or disabled
values. This changes __enable_mmu() function to handle complete acceptable
range of values (depending on whether the field is signed or unsigned) now
represented with ID_AA64MMFR0_TGRAN_SUPPORTED_[MIN..MAX] pair. While here,
also fix similar situations in EFI stub and KVM as well.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-efi@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Anshuman Khandual <redacted>
---
arch/arm64/include/asm/sysreg.h | 20 ++++++++++++++------
arch/arm64/kernel/head.S | 6 ++++--
arch/arm64/kvm/reset.c | 23 ++++++++++++-----------
drivers/firmware/efi/libstub/arm64-stub.c | 2 +-
4 files changed, 31 insertions(+), 20 deletions(-)
The TGRAN2 fields doesn't quite follow the usual ID scheme rules, so how
do we deteremine the max value? Does the ARM ARM say anything in
particular about them, like we do for some of the PMU ID fields?
Did not find anything in ARM ARM, regarding what scheme TGRAN2 fields
actually follow. I had arrived at more restrictive 0x7 value, like the
usual signed fields as the TGRAN4 fields definitely do not follow the
unsigned ID scheme. Would restricting max value to 0x3 (i.e LPA2) be a
better option instead ?
Otherwise, this patch looks correct to me.
Thanks,
Mark.
From: Will Deacon <will@kernel.org> Date: 2021-03-08 13:31:54
On Sun, Mar 07, 2021 at 05:24:21PM +0530, Anshuman Khandual wrote:
On 3/5/21 8:21 PM, Mark Rutland wrote:
quoted
On Fri, Mar 05, 2021 at 08:06:09PM +0530, Anshuman Khandual wrote:
quoted
From: James Morse <james.morse@arm.com>
As per ARM ARM DDI 0487G.a, when FEAT_LPA2 is implemented, ID_AA64MMFR0_EL1
might contain a range of values to describe supported translation granules
(4K and 16K pages sizes in particular) instead of just enabled or disabled
values. This changes __enable_mmu() function to handle complete acceptable
range of values (depending on whether the field is signed or unsigned) now
represented with ID_AA64MMFR0_TGRAN_SUPPORTED_[MIN..MAX] pair. While here,
also fix similar situations in EFI stub and KVM as well.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-efi@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Anshuman Khandual <redacted>
---
arch/arm64/include/asm/sysreg.h | 20 ++++++++++++++------
arch/arm64/kernel/head.S | 6 ++++--
arch/arm64/kvm/reset.c | 23 ++++++++++++-----------
drivers/firmware/efi/libstub/arm64-stub.c | 2 +-
4 files changed, 31 insertions(+), 20 deletions(-)
The TGRAN2 fields doesn't quite follow the usual ID scheme rules, so how
do we deteremine the max value? Does the ARM ARM say anything in
particular about them, like we do for some of the PMU ID fields?
Did not find anything in ARM ARM, regarding what scheme TGRAN2 fields
actually follow. I had arrived at more restrictive 0x7 value, like the
usual signed fields as the TGRAN4 fields definitely do not follow the
unsigned ID scheme. Would restricting max value to 0x3 (i.e LPA2) be a
better option instead ?
I don't think it helps much, as TGRAN64_2 doesn't even define 0x3.
So I think this patch is probably the best we can do, but the Arm ARM could
really do with describing the scheme here.
Will
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The TGRAN2 fields doesn't quite follow the usual ID scheme rules, so how
do we deteremine the max value? Does the ARM ARM say anything in
particular about them, like we do for some of the PMU ID fields?
Did not find anything in ARM ARM, regarding what scheme TGRAN2 fields
actually follow. I had arrived at more restrictive 0x7 value, like the
usual signed fields as the TGRAN4 fields definitely do not follow the
unsigned ID scheme. Would restricting max value to 0x3 (i.e LPA2) be a
better option instead ?
I don't think it helps much, as TGRAN64_2 doesn't even define 0x3.
So I think this patch is probably the best we can do, but the Arm ARM could
really do with describing the scheme here.
I agree, and I've filed a ticket internally to try to get this cleaned
up.
I suspect that the answer is that these are basically unsigned, with
0x2-0xf indicating presence, but I can't guarantee that.
Thanks,
Mark.
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From: Marc Zyngier <maz@kernel.org> Date: 2021-03-08 14:43:00
On Fri, 05 Mar 2021 14:36:09 +0000,
Anshuman Khandual [off-list ref] wrote:
quoted hunk
From: James Morse <james.morse@arm.com>
As per ARM ARM DDI 0487G.a, when FEAT_LPA2 is implemented, ID_AA64MMFR0_EL1
might contain a range of values to describe supported translation granules
(4K and 16K pages sizes in particular) instead of just enabled or disabled
values. This changes __enable_mmu() function to handle complete acceptable
range of values (depending on whether the field is signed or unsigned) now
represented with ID_AA64MMFR0_TGRAN_SUPPORTED_[MIN..MAX] pair. While here,
also fix similar situations in EFI stub and KVM as well.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: James Morse <james.morse@arm.com>
Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: kvmarm@lists.cs.columbia.edu
Cc: linux-efi@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Anshuman Khandual <redacted>
---
arch/arm64/include/asm/sysreg.h | 20 ++++++++++++++------
arch/arm64/kernel/head.S | 6 ++++--
arch/arm64/kvm/reset.c | 23 ++++++++++++-----------
drivers/firmware/efi/libstub/arm64-stub.c | 2 +-
4 files changed, 31 insertions(+), 20 deletions(-)
@@ -312,15 +312,18 @@ int kvm_set_ipa_limit(void)switch(cpuid_feature_extract_unsigned_field(mmfr0,tgran_2)){default:-case1:+caseID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE:kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");return-EINVAL;-case0:+caseID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT:kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n");break;-case2:+caseID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN...ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX:kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n");break;+default:+kvm_err("Unsupported value for TGRAN_2, giving up\n");+return-EINVAL;}kvm_ipa_limit=id_aa64mmfr0_parange_to_phys_shift(parange);
Otherwise:
Acked-by: Marc Zyngier <maz@kernel.org>
M.
--
Without deviation from the norm, progress is not possible.
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@@ -312,15 +312,18 @@ int kvm_set_ipa_limit(void)switch(cpuid_feature_extract_unsigned_field(mmfr0,tgran_2)){default:-case1:+caseID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE:kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");return-EINVAL;-case0:+caseID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT:kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n");break;-case2:+caseID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN...ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX:kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n");break;+default:+kvm_err("Unsupported value for TGRAN_2, giving up\n");+return-EINVAL;}kvm_ipa_limit=id_aa64mmfr0_parange_to_phys_shift(parange);
Otherwise:
Acked-by: Marc Zyngier <maz@kernel.org>
Anshuman -- please can you spin a v2 with the switch syntax as suggested
above by Marc?
Will
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@@ -312,15 +312,18 @@ int kvm_set_ipa_limit(void)switch(cpuid_feature_extract_unsigned_field(mmfr0,tgran_2)){default:-case1:+caseID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE:kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");return-EINVAL;-case0:+caseID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT:kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n");break;-case2:+caseID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN...ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX:kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n");break;+default:+kvm_err("Unsupported value for TGRAN_2, giving up\n");+return-EINVAL;}kvm_ipa_limit=id_aa64mmfr0_parange_to_phys_shift(parange);
Otherwise:
Acked-by: Marc Zyngier <maz@kernel.org>
Anshuman -- please can you spin a v2 with the switch syntax as suggested
above by Marc?