Thread (9 messages) flat view 9 messages, 2 authors, 2021-01-25

Re: [PATCH] ARM: decompressor: cover BSS in cache clean and reorder with MMU disable on v7

From: Russell King - ARM Linux admin <linux@armlinux.org.uk>
Date: 2021-01-24 16:20:34

On Sun, Jan 24, 2021 at 04:45:14PM +0100, Ard Biesheuvel wrote:
Fair enough. I don't think we will ever be able to get to the bottom of this.
DDI0406 does say that the data accesses will have a "strongly ordered"
memory type, and that the unexpected cache hit behaviour is
implementation defined. That leaves the door open for different
behaviours at different cache levels in a SoC, especially when each
cache level is designed by a different entity.

So, without a greater understanding of how each level of cache operates
and how they interact with each other, I don't think there's much hope
of knowing definitely what is causing the observed behaviour. Hence, we
agree.
So on the basis that this patch adds back a full cache
clean+invalidate that was inadvertently removed by my previous patch,
I think we should apply this patch. GIven that this change can be
traced back to commit 401b368caaecdce1cf8f05bab448172752230cb0, we
should probably include

Fixes: 401b368caaec ("ARM: decompressor: switch to by-VA cache
maintenance for v7 cores")

Are you on board with that?
Yes, I think that's definitely the commit which introduced this bug.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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