On 22-01-21, 17:31, Dmitry Osipenko wrote:

This may not be true for all kinds of hardware, a display controller is
one example. If display's pixclock is raised before the memory bandwidth
of the display's memory client, then display controller may get a memory
underflow since it won't be able to fetch memory fast enough and it's
not possible to pause data transmission to display panel, hence display
panel may get out of sync and a full hardware reset will be needed in
order to recover. At least this is the case for NVIDIA Tegra SoCs.

Hmm, but I expected that the request for more data will only come after the
opp-set-rate has finished and not in between. May be I am wrong. There is
nothing wrong in doing it the regulator way if required.

I guess it's not a real problem for any of OPP API users right now, but
this is something to keep in mind.

Sure, I am not against it. Just that we thought it isn't worth the code.

-- 
viresh

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