[RFC PATCH 1/2] arm64: dts: imx8mm: Fix the ENET interrupts order

According to Documentation/devicetree/bindings/net/fsl-fec.txt, when
interrupt-names is not passed the following interrupt order is assumed:

  __Number of interrupts__   __Default__
	1			"int0"
	2			"int0", "pps"
	3			"int0", "int1", "int2"
	4			"int0", "int1", "int2", "pps"

In the current imx8mm.dtsi this translates to:

- int0 ---> IRQ 118
- int1 ---> IRQ 119
- int2 ---> IRQ 120

However, just like i.MX7, i.MX8MM uses the following ENET irq mapping:

- int0 ---> IRQ 120
- int1 ---> IRQ 118
- int2 ---> IRQ 119

Fix it by passing the interrupt-names property with the correct mapping.

Tested networking on a imx8mm-evk board successfully.

Signed-off-by: Fabio Estevam <festevam@gmail.com>
---
Hi Fugang,

Could you please help review this RFC series?

My understanding is that the i.MX8M class of products are derived from
i.MX7 from an ENET IRQ mapping perspective. (i.MX8QXP also uses the
same i.MX7 mapping by the way). The Reference Manual also seems to
indicate the same, but the ENET IRQ naming differs a bit between the
i.MX7 and i.MX8MM RM's.

If this is correct, then I plan to also fix i.MX8MQ, i.MX8MN and i.MX8MP dtsi
files.

My initial goal was to add the pps irq (patch 2/2), but then I noticed
the potential irq mismatch and now it is a two patch series.

Thanks

 arch/arm64/boot/dts/freescale/imx8mm.dtsi | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index aaf6e71101a1..551afc270fb7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi

@@ -844,9 +844,10 @@
 			fec1: ethernet@30be0000 {
 				compatible = "fsl,imx8mm-fec", "fsl,imx6sx-fec";
 				reg = <0x30be0000 0x10000>;
-				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
-					     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+				interrupt-names = "int0", "int1", "int2";
+				interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+					<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
 				clocks = <&clk IMX8MM_CLK_ENET1_ROOT>,
 					 <&clk IMX8MM_CLK_ENET1_ROOT>,
 					 <&clk IMX8MM_CLK_ENET_TIMER>,

-- 
2.17.1


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