---
 drivers/gpu/drm/vc4/vc4_hdmi.c |  9 +++++++++
 drivers/gpu/drm/vc4/vc4_regs.h |  3 +++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/vc4/vc4_hdmi.c b/drivers/gpu/drm/vc4/vc4_hdmi.c
index f56a718a3643..37463b016b47 100644
--- a/drivers/gpu/drm/vc4/vc4_hdmi.c
+++ b/drivers/gpu/drm/vc4/vc4_hdmi.c

@@ -325,6 +325,12 @@ static void vc4_hdmi_encoder_post_crtc_disable(struct drm_encoder *encoder)
        struct vc4_hdmi *vc4_hdmi = encoder_to_vc4_hdmi(encoder);

        HDMI_WRITE(HDMI_RAM_PACKET_CONFIG, 0);
+
+       HDMI_WRITE(HDMI_VID_CTL, HDMI_READ(HDMI_VID_CTL) |
+                  VC4_HD_VID_CTL_CLRRGB | VC4_HD_VID_CTL_CLRSYNC);
+
+       HDMI_WRITE(HDMI_VID_CTL,
+                  HDMI_READ(HDMI_VID_CTL) | VC4_HD_VID_CTL_BLANKPIX);
 }

 static void vc4_hdmi_encoder_post_crtc_powerdown(struct drm_encoder *encoder)

@@ -563,6 +569,9 @@ static void vc4_hdmi_encoder_post_crtc_enable(struct drm_encoder *encoder)
                   (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
                   (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));

+       HDMI_WRITE(HDMI_VID_CTL,
+                  HDMI_READ(HDMI_VID_CTL) & ~VC4_HD_VID_CTL_BLANKPIX);
+
        if (vc4_encoder->hdmi_monitor) {
                HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
                           HDMI_READ(HDMI_SCHEDULER_CONTROL) |

diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index d1e8961edaa0..30af52b406f1 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h

@@ -723,6 +723,9 @@
 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET    BIT(29)
 # define VC4_HD_VID_CTL_VSYNC_LOW              BIT(28)
 # define VC4_HD_VID_CTL_HSYNC_LOW              BIT(27)
+# define VC4_HD_VID_CTL_CLRSYNC                        BIT(24)
+# define VC4_HD_VID_CTL_CLRRGB                 BIT(23)
+# define VC4_HD_VID_CTL_BLANKPIX               BIT(18)

 # define VC4_HD_CSC_CTL_ORDER_MASK             VC4_MASK(7, 5)
 # define VC4_HD_CSC_CTL_ORDER_SHIFT            5
--

git-series 0.9.1