From: Sven Van Asbroeck <redacted> Sent: Tuesday, June 30, 2020 11:24 PM

Andy, Fabio,

On Tue, Jun 30, 2020 at 2:36 AM Andy Duan [off-list ref] wrote:

quoted

Sven, no matter PHY supply 125Mhz clock to pad or not,  GPR5[9] is to
select RGMII gtx clock source from:
- 0 Clock from pad
- 1 Clock from PLL

Since i.MX6QP can internally supply clock to MAC, we can set GPR5[9] bit by

default.

That's true. But on the sabresd I notice that the PHY's ref_clk output is from
CLK_25M.
The default ref_clk freq for that PHY is 25 MHz, and I don't see anyone change
the default in the devicetree. I also see that a 25 MHz crystal is fitted, which
also suggests 25 Mhz output.

On the imx6, the default ref_clk frequency from ANATOP is 50Mhz. I don't see
anyone change that default in the devicetree either.

So is it possible that, when we switch GPR5[9] on, the external 25MHz clock is
replaced by the internal 50MHz clock? If so, I'm not sure it'll work...?

Fabio, the reason is that you don't update uboot that why we cannot reproduce
the issue on imx6qp sabresd.

Sven, uboot board file set the clock rate.
board/freescale/mx6sabresd/mx6sabresd.c:
        if (is_mx6dqp()) {
                int ret;

                /* select ENET MAC0 TX clock from PLL */
                imx_iomux_set_gpr_register(5, 9, 1, 1);
                ret = enable_fec_anatop_clock(0, ENET_125MHZ);
                if (ret)
                    printf("Error fec anatop clock settings!\n");
        }

Sven, to avoid to depend on uboot setting, for the patch, it is better to bind
below change for dts (even if non imx6qp, ptp clock can be set to 125Mhz):

--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi

@@ -202,6 +202,8 @@
 &fec {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet>;
+       assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF>;
+       assigned-clock-rates = <125000000>;
        phy-mode = "rgmii-id"; 

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