Re: [PATCH V3 04/16] arm64/cpufeature: Introduce ID_PFR2 CPU register
From: Mark Rutland <mark.rutland@arm.com>
Date: 2020-05-05 12:49:59
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On Tue, May 05, 2020 at 01:12:39PM +0100, Will Deacon wrote:
On Tue, May 05, 2020 at 12:50:54PM +0100, Mark Rutland wrote:quoted
On Tue, May 05, 2020 at 12:27:19PM +0100, Will Deacon wrote:quoted
On Tue, May 05, 2020 at 12:16:07PM +0100, Mark Rutland wrote:quoted
On Tue, May 05, 2020 at 12:12:41PM +0100, Will Deacon wrote:quoted
On Sat, May 02, 2020 at 07:03:53PM +0530, Anshuman Khandual wrote:quoted
diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index e5317a6367b6..c977449e02db 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h@@ -153,6 +153,7 @@ #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0) #define SYS_MVFR1_EL1 sys_reg(3, 0, 0, 3, 1) #define SYS_MVFR2_EL1 sys_reg(3, 0, 0, 3, 2) +#define SYS_ID_PFR2_EL1 sys_reg(3, 0, 0, 3, 4)nit: but please group these defines by name rather than encoding.So far we've *always* grouped these by encoding in this file, so can we keep things that way for now? Otherwise we're inconsistent with both schemes.Hmm, but it's really hard to read sorted that way and we'll end up with duplicate definitions like we had for some of the field offsets already.I appreciate that, and don't disagree that the current scheme is not obvious. I just want to ensure that we don't make things less consistent, and if we're going to change the scheme in order to make that easier, it should be a separate patch. There'll be other changes like MMFR4_EL1, and we should probably add a comment as to what the policy is either way (e.g. if we're just grouping at the top level, or if that should be sorted too).Ok, I added a comment below.
Thanks! Acked-by: Mark Rutland <mark.rutland@arm.com> Mark.
quoted hunk ↗ jump to hunk
Will --->8 commit be7ab6a6cdb0a6d7b10883094c2adf96f5d4e1e8 Author: Will Deacon [off-list ref] Date: Tue May 5 13:08:02 2020 +0100 arm64: cpufeature: Group indexed system register definitions by name Some system registers contain an index in the name (e.g. ID_MMFR<n>_EL1) and, while this index often follows the register encoding, newer additions to the architecture are necessarily tacked on the end. Sorting these registers by encoding therefore becomes a bit of a mess. Group the indexed system register definitions by name so that it's easier to read and will hopefully reduce the chance of us accidentally introducing duplicate definitions in the future. Signed-off-by: Will Deacon [off-list ref]diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 2dd3f4ca9780..194684301df0 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h@@ -105,6 +105,10 @@ #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) +/* + * System registers, organised loosely by encoding but grouped together + * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. + */ #define SYS_OSDTRRX_EL1 sys_reg(2, 0, 0, 0, 2) #define SYS_MDCCINT_EL1 sys_reg(2, 0, 0, 2, 0) #define SYS_MDSCR_EL1 sys_reg(2, 0, 0, 2, 2)@@ -140,6 +144,7 @@ #define SYS_ID_MMFR1_EL1 sys_reg(3, 0, 0, 1, 5) #define SYS_ID_MMFR2_EL1 sys_reg(3, 0, 0, 1, 6) #define SYS_ID_MMFR3_EL1 sys_reg(3, 0, 0, 1, 7) +#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) #define SYS_ID_ISAR0_EL1 sys_reg(3, 0, 0, 2, 0) #define SYS_ID_ISAR1_EL1 sys_reg(3, 0, 0, 2, 1)@@ -147,7 +152,6 @@ #define SYS_ID_ISAR3_EL1 sys_reg(3, 0, 0, 2, 3) #define SYS_ID_ISAR4_EL1 sys_reg(3, 0, 0, 2, 4) #define SYS_ID_ISAR5_EL1 sys_reg(3, 0, 0, 2, 5) -#define SYS_ID_MMFR4_EL1 sys_reg(3, 0, 0, 2, 6) #define SYS_ID_ISAR6_EL1 sys_reg(3, 0, 0, 2, 7) #define SYS_MVFR0_EL1 sys_reg(3, 0, 0, 3, 0)
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